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Samsung semiconductor |
K5A3x40YT(B)C
Preliminary
MCP MEMORY
Document Title
Multi-Chip Package MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
Remark
November 6, 2002 Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 0.0
November 2002
K5A3x40YT(B)C
Preliminary
MCP MEMORY
Multi-Chip Package MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
FEATURES
• Power Supply voltage : 2.7V to 3.3V
• Organization
- Flash : 4,194,304 x 8 / 2,097,152 x 16 bit
- SRAM : 524,288 x 8 / 262,144 x 16 bit
• Access Time (@2.7V)
- Flash : 70 ns, SRAM : 55 ns
• Power Consumption (typical value)
- Flash Read Current : 14 mA (@5MHz)
Program/Erase Current : 15 mA
Standby mode/Autosleep mode : 5 µA
Read while Program or Read while Erase : 25 mA
- SRAM Operating Current : 20 mA
Standby Current : 0.5 µA
• Secode(Security Code) Block : Extra 64KB Block (Flash)
• Block Group Protection / Unprotection (Flash)
• Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb
• Flash Endurance : 100,000 Program/Erase Cycles Minimum
• SRAM Data Retention : 1.5 V (min.)
• Industrial Temperature : -40°C ~ 85°C
• Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch
1.2mm(max.) Thickness
GENERAL DESCRIPTION
The K5A3x40YT(B)C featuring single 3.0V power supply is a
Multi Chip Package Memory which combines 32Mbit Dual Bank
Flash and 4Mbit fCMOS SRAM.
The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit
and 4Mbit SRAM is organized as 512K x8 or 256K x16 bit. The
memory architecture of flash memory is designed to divide its
memory arrays into 71 blocks and this provides highly flexible
erase and program capability. This device is capable of reading
data from one bank while programming or erasing in the other
bank with dual bank organization.
The Flash memory performs a program operation in units of 8 bits
(Byte) or 16 bits (Word) and erases in units of a block. Single or
multiple blocks can be erased. The block erase operation is com-
pleted for typically 0.7sec.
The 4Mbit SRAM supports low data retention voltage for battery
backup operation with low data retention current.
The K5A3x40YT(B)C is suitable for the memory of mobile com-
munication system to reduce mount area. This device is available
in 69-ball TBGA Type package.
BALL CONFIGURATION
1 2 3 4 5 6 7 8 9 10
A N.C
N.C N.C
N.C
B N.C
A7
LB
WP/
ACC
WE
A8
A11
C A3 A6 UB RESET CS2S A19 A12 A15
D A2 A5 A18 RY/BY A20 A9 A13 N.C
E N.C A1 A4 A17
A10 A14 N.C N.C
F N.C A0 Vss DQ1
DQ6 SA A16 N.C
G
CEF
OE
DQ9 DQ3
DQ4
DQ13
DQ15
/A-1
BYTEF
H CS1S DQ0 DQ10 VccF VccS DQ12 DQ7 Vss
J DQ8 DQ2 DQ11 BYTES DQ5 DQ14
K N.C
N.C N.C
N.C
69 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
BALL DESCRIPTION
Ball Name
A0 to A17
A-1, A18 to A20
DQ0 to DQ15
RESET
WP/ACC
Description
Address Input Balls (Common)
Address Input Balls (Flash Memory)
Data Input/Output Balls (Common)
Hardware Reset (Flash Memory)
Write Protection / Acceleration Program
(Flash Memory)
VccS
VccF
Vss
UB
LB
BYTES
BYTEF
SA
CEF
CS1S
CS2S
WE
OE
RY/BY
N.C
Power Supply (SRAM)
Power Supply (Flash Memory)
Ground (Common)
Upper Byte Enable (SRAM)
Lower Byte Enable (SRAM)
BYTES Control (SRAM)
BYTEF Control (Flash Memory)
Address Inputs (SRAM)
Chip Enable (Flash Memory)
Chip Enable (SRAM Low Active)
Chip Enable (SRAM High Active)
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
- 2 - Revision 0.0
November 2002
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