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PO74HSTL85331A 반도체 회로 부품 판매점

3.3V 1:4 Crystal Oscillator/ Differential Clock or Data Fanout Buffer



Potato Semiconductor Corporation 로고
Potato Semiconductor Corporation
PO74HSTL85331A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PO74HSTL85331A
3.3V 1:4 Crystal Oscillator/
Differential Clock or Data Fanout Buffer
700MHz HSTL Potato Chip
03/01/07
FEATURES:
DESCRIPTION:
. Patented Technology
The PO74HSTL85331A is a low skew, high performance
. Four HSTL differential outputs
1-to-4 Crystal Oscillator/Differential-to-3.3V HSTL
. Selectable differential CLK, nCLK or crystal inputs fanout buffer of High Performance Clock Solutions from
. CLK, nCLK pair can accept the following differential PotatoSemi. The PO74HSTL85331A has selectable
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL differential clock or crystal inputs. The CLK, nCLK pair
. Operating frequency up to 700MHz with 2pf load
can accept most standard differential input levels. The
. Operating frequency up to 550MHz with 5pf load
clock enable is internally synchronized to eliminate runt
. Operating frequency up to 400MHz with 15pf load pulses on the outputs during asynchronous
. Very low output pin to pin skew < 50ps
assertion/deassertion of the clock enable pin.
. 3.3-ns propagation delay (typical)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
Guaranteed output and part-to-part skew characteristics
make the PO74HSTL85331A ideal for those applications
demanding well defined performance and repeatability.
Pin Configuration
VEE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VCC
17 Q1
16 nQ1
15 Q2
14 nQ2
13 VCC
12 Q3
11 nQ3
Logic Block Diagram
CLK_EN
CLK
nCLK
XTAL1
XTAL2
CLK_SEL
0
1
D
Q
LE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Copyright © Potato Semiconductor Corporation


PO74HSTL85331A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PO74HSTL85331A
3.3V 1:4 Crystal Oscillator/
Differential Clock or Data Fanout Buffer
700MHz HSTL Potato Chip
08/03/06
Pin Definitions
Nu m b e r
Na m e
Typ e
De s c rip tio n
1 VEE Powe r
GND Pin
S ynchronizing clock e na ble. Whe n HIGH, clock outputs follows clock input.
2 CLK_EN Input P ullu p Whe n LOW, Q outputs a re force d low, nQ outputs a re force d high.
LVCMOS / LVTTL inte rfa ce leve ls.
3
CLK_S EL
Input
P ulldown
Clock s e le ct input. Whe n LOW, s e le cts CLK, nCLK input.
Whe n HIGH, s e le cts XTAL input. LVCMOS / LVTTL inte rfa ce leve ls.
4
CLK
Input P ulldown Non-inve rting diffe re ntia l clock input.
5
nCLK
Input P ullu p Inve rting diffe re ntia l clock input.
6
XTAL1
Inpu t P ulldown Crys ta l os cilla tor input.
7
XTAL2
Inpu t P ullu p Crys ta l os cilla tor input.
8, 9 nc Unus ed
No conne ct.
10, 13, 18
11, 12
VCC
nQ3, Q3
Powe r
Output
Pos itive s upply pins.
Diffe re ntia l clock outputs. HSTL inte rfa ce leve ls.
14, 15
nQ2, Q2 Output
Diffe re ntia l clock outputs. HSTL inte rfa ce leve ls.
16, 17
nQ1, Q1 Output
Diffe re ntia l clock outputs. HSTL inte rfa ce leve ls.
19, 20
nQ0, Q0 Output
Diffe re ntia l clock outputs. HSTL inte rfa ce leve ls.
NOTE: P ullup a nd P ulldown re fe r to inte rna l input re s is tors. S e e Ta ble 2, P in cha ra cte ris tics, for typica l va lue s.
Function Table
In p u ts
Outputs
CLK_EN
CLK_S EL
S e le c te d S o u rc e
Q0:Q3
nQ0:nQ3
0
0
CLK, nCLK
Dis a ble d; LOW
Dis a ble d; HIGH
0
1
XTAL1, XTAL2
Dis a ble d; LOW
Dis a ble d; HIGH
1
0
CLK, nCLK
Ena ble d
Ena ble d
1
1
XTAL1, XTAL2
Ena ble d
Ena ble d
Afte r CLK_EN switche s, the clock outputs a re dis a ble d or e na ble d folowing a ris ing a nd fa lling input clock or
crys ta l os cilla tor e dge a s s hown in Figure 1.
In the a ctive mode, the s ta te of the outputs a re a function of the CLK, nCLK a nd XTAL1, XTAL2 inputs a s de s cribe d
in Ta ble 3B.
Pin Characteristics
Symbol
C IN
RP ULLUP
RP ULLDOWN
Pa ra m e ter
Input Ca pa cita nce
Input P ullup Re s is tor
Input P ulldown Re s is tor
Te s t Co n d itio n s
Min imu m
Typ ic a l
4
88
88
Ma ximu m
Un it s
pF
K
K
2
Copyright © Potato Semiconductor Corporation




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3.3V 1:4 Crystal Oscillator/ Differential Clock or Data Fanout Buffer - Potato Semiconductor Corporation