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PDF AZ100LVEL16VV Data sheet ( Hoja de datos )
| Número de pieza | AZ100LVEL16VV | |
| Descripción | Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer | |
| Fabricantes | Arizona Microtek | |
| Logotipo |  |
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ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
PACKAGE AVAILABILITY
• High Bandwidth for ≥1GHz
• Similar Operation as AZ100EL16VR
except with selectable data input pairs
• Operating Range of 3.0V to 5.5V
• Minimizes External Components
• Available in a 3x3mm MLP Package
• S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE
PART NUMBER MARKING NOTES
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead (Pb) AZ100LVEL16VVL+ 16K
1,2
Free <Date Code>
DIE
AZ100LVEL16VVXP N/A
3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code format: “Y” for year followed by “WW” for week.
3 Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D¯¯0 is selected. When the
SEL pin is HIGH data from the D1/D¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
the Q/Q¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately
connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is
recommended.
Each Q/Q¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
pull-down current of the Q/Q¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
1 page  
AZ100LVEL16VV
30 200.00
25 150.00
S21 MAG
20 100.00
S21 PHASE
15 50.00
10
50
0.00
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
S21, D0/D1 to Q¯ , 50 Ω AC load on Q¯
0.8 30.00
0.7 25.00
0.6 20.00
0.5 15.00
0.4 10.00
0.3 5.00
0.2
50
0.00
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
S22 MAG
S22 PHASE
S22, D0/D1 to Q¯ , 50 Ω AC load on Q¯
April 2007 * REV - 9
www.azmicrotek.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AZ100LVEL16VV.PDF ] | |
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