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PDF ICS831742I Data sheet ( Hoja de datos )
| Número de pieza | ICS831742I | |
| Descripción | 4:2 Differential Clock/Data Multiplexer | |
| Fabricantes | Integrated Device Technology | |
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4:2 Differential Clock/Data
Multiplexer
ICS831742I
DATA SHEET
General Description
The ICS831742I is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals. The
device has four differential, selectable clock/data inputs. The selected
input signal is distributed to two low-skew differential HCSL outputs.
Each input pair accepts HCSL, LVDS and LVPECL levels. The
ICS831742I is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the ICS831742I ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The ICS831742I supports the clock multiplexing and
distribution of PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and
Gen 3 (8 Gb/s) clock signals.
Features
• 4:2 differential clock/data multiplexer with fanout
• Four selectable, differential input pairs
• Each differential input pair can accept the following levels: HCSL,
LVDS and LVPECL
• Two differential HCSL output pairs
• Maximum input/output clock frequency: 700MHz
• Maximum input/output data rate: 1400Mb/s (NRZ)
• LVCMOS interface levels for all control inputs
• PCI Express (2.5Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
jitter compliant
• Input skew: 110ps max
• Part-to-part skew: 225ps max
• Full 3.3V supply voltage
• Available in lead-free (RoHS 6)
• -40°C to 85°C ambient operating temperature
Block Diagram
IREF
CLK0 Pulldown
nCLK0 Pullup/down
Pulldown
CLK1
nCLK1 Pullup/down
Pulldown
CLK2
nCLK2 Pullup/down
Pulldown
CLK3
nCLK3 Pullup/down
SEL1 Pulldown
SEL0 Pulldown
nOEA Pullup
nOEB Pullup
00
01
10
11
QA
nQA
QB
nQB
Pin Assignment
GND
CLK0
nCLK0
VDD
CLK1
nCLK1
CLK2
nCLK2
GND
CLK3
nCLK3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24 SEL1
23 IREF
22 SEL0
21 VDD
20 nQB
19 QB
18 nQA
17 QA
16 VDD
15 GND
14 nOEB
13 nOEA
ICS831742AGI
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS831742AGI JULY 10, 2012
1 ©2012 Integrated Device Technology, Inc.
1 page  
ICS831742I Data Sheet
4:2 DIFFERENTIAL CLOCK/DATA MULTIPLEXER
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
tj
(PCIe Gen 1)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
tREFCLK_HF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_LF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ= 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 100MHz Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 100MHz Input
Low Band: 10kHz - 1.5MHz
ƒ= 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum Typical
10
1
0.05
0.2
Maximum
21
2.5
0.2
0.8
PCIe Industry
Specification
86
3.1
3.0
0.8
Units
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Measurements performed with a PCI Express compliant input source. For additional information,
refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS831742AGI JULY 10, 2012
5 ©2012 Integrated Device Technology, Inc.
5 Page 
ICS831742I Data Sheet
4:2 DIFFERENTIAL CLOCK/DATA MULTIPLEXER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter HiPerClockS LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
CLK
nCLK
Differential
R1 R2
84Ω 84Ω
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
2.5V
*R3 33
Zo = 50Ω
Zo = 50Ω
HCSL
*R4 33
*Optional – R3 and R4 can be 0Ω
R1
50
3.3V
CLK
nCLK
Differential
R2 Input
50
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
ICS831742AGI JULY 10, 2012
11 ©2012 Integrated Device Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet ICS831742I.PDF ] | |
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