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PDF ICS83056I Data sheet ( Hoja de datos )
| Número de pieza | ICS83056I | |
| Descripción | SINGLE-ENDED MULTIPLEXER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS83056I is a low skew, 6:1, Single-ended • 6:1 single-ended multiplexer
ICS
HiPerClockS™
Multiplexer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
•
Q
nominal
output
impedance:
7Ω
(V
DDO
=
3
.3V)
ICS. The ICS83056I has six selectable single- • Maximum output frequency: 250MHz
ended clock inputs and one single-ended clock
output. The output has a VDDO pin which may be set at 3.3V,
2.5V, or 1.8V, making the device ideal for use in voltage transla-
tion applications. An output enable pin places the output in
www.DataSheeat4Uh.igcohmimpedance state which may be useful for testing or
• Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V
• Input skew: 225ps (maximum), VDD = VDDO = 3.3V
• Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V
debug. The device operates up to 250MHz and is packaged • Operating supply modes:
in a 16 TSSOP.
V /V
DD DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
SEL2
SEL1
SEL0
OE
83056AGI
PIN ASSIGNMENT
Q1
1 6 VDDO
nc 2 15 CLK0
OE 3 14 SEL0
nc 4 13 CLK1
GND 5
12 VDD
CLK5 6 11 CLK2
Q SEL2 7 10 SEL1
CLK4 8
9 CLK3
ICS83056I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 18, 2006
1 page  
Integrated
Circuit
Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tpHL
tsk(i)
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
250 MHz
2.5 2.8
3.1 ns
2.6 2.8
3.0 ns
45 150 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3
400 ps
www.DataSheet4t U/.ctom
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
45
500 ps
55 %
MUXISOL MUX Isolation
@ 100MHz
45
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
dB
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tpLH
tpHL
tsk(i)
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
250
2.7 3.2 3.8
2.8 3.3 3.8
50 150
tsk(pp) Part-to-Part Skew; NOTE 2, 3
475
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
45
700
55
MUXISOL MUX Isolation
@ 100MHz
45
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
Units
MHz
ns
ns
ps
ps
ps
%
dB
83056AGI
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 18, 2006
5 Page 
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
www.DataSheet4U.com
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
83056AGI
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N 16
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.10
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
α 0° 8°
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 18, 2006
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