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Integrated Circuit Systems |
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83054I-01
4-BIT, 2:1,
SINGLE-ENDED MULTIPLEXER
GENERAL DESCRIPTION
The ICS83054I-01 is a 4-bit, 2:1, Single-ended Mul-
ICS tiplexer and a member of the HiPerClockS™fam-
HiPerClockS™ ily of High Performance Clock Solutions from ICS.
The ICS83054I-01 has two selectable single-ended
clock inputs and four single-ended clock outputs.
The output has a VDDO pin which may be set at 3.3V, 2.5V, or
1.8V, making the device ideal for use in voltage translation ap-
plications. An output enable pin places the output in
www.DataSheeat4Uh.igcohmimpedance state which may be useful for testing or
debug. Possible applications include systems with up to four
transceivers which need to be independently set for different
rates. For example, a board may have four transceivers, each
of which need to be independently configured for 1 Gigabit
Ethernet or 1 Gigabit Fibre Channel rates. Another possible
application may require the ports to be independently set for
FEC (Forward Error Correction) or non-FEC rates. The device
operates up to 250MHz and is packaged in a 16 TSSOP.
FEATURES
• 4-bit, 2:1 single-ended multiplexer
•
Nominal
output
impedance:
15Ω
(V
DDO
=3
.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 2.5ns (typical)
• Input skew: 45ps (typical)
• Part-to-part skew: TBD
• Additive phase jitter, RMS (12KHz - 20MHz):
0.07ps (typical)
• Operating supply modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
SEL0 Pulldown
CLK0
CLK1
Pulldown
Pulldown
0
1
SEL3 Pulldown
OE Pullup
0
1
PIN ASSIGNMENT
SEL3 1 16 SEL0
Q3 2 15 Q0
VDDO 3
1 4 VDDO
GND 4 13 GND
Q0 Q2 5 12 Q1
SEL2 6 11 SEL1
CLK1 7 10 CLK0
VDD 8
9 OE
ICS83054I-01
16-Lead TSSOP
Q3 4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
1
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83054I-01
4-BIT, 2:1,
SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 6
11, 16
SEL3, SEL2,
SEL1, SEL0
Input
Pulldown
Clock select inputs. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
2, 5, 9, 12, 15 Q3, Q2, Q1, Q0 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
3, 14
4, 13
VDDO
GND
Power
Power
Output supply pins.
Power supply ground.
7, 10
www.DataSheet4U.com
8
9
CLK1, CLK0
VDD
OE
Input
Power
Input
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Core supply pin.
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
R
PULLDOWN
CPD
ROUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
11 pF
15 Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
SEL3
0
0
0
1
1
1
Control Inputs
SEL2
SEL1
00
00
01
•
•
•
10
11
11
SEL0
0
1
0
1
0
1
Q3
CLK0
CLK0
CLK0
CLK1
CLK1
CLK1
Outputs
Q2 Q1
CLK0
CLK0
CLK0
CLK0
CLK0
CLK1
•
•
•
CLK1
CLK0
CLK1
CLK1
CLK1
CLK1
Q0
CLK0
CLK1
CLK0
CLK1
CLK0
CLK1
83054AGI-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 24, 2004
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