파트넘버.co.kr ICS83054I 데이터시트 PDF


ICS83054I 반도체 회로 부품 판매점

SINGLE-ENDED MULTIPLEXER



Integrated Circuit Systems 로고
Integrated Circuit Systems
ICS83054I 데이터시트, 핀배열, 회로
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, SINGLE-ENDED MULTIPLEXER
GENERAL DESCRIPTION
The ICS83054I is a low skew, 4:1, Single-
ICS ended Multiplexer and a member of the
HiPerClockS™ HiPerClockS ™ family of High Perfor mance
Clock Solutions from ICS. The ICS83054I
has four selectable single-ended clock inputs
and one single-ended clock output. The output has a
VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making
the device ideal for use in voltage translation applications.
www.DataSheeAt4nU.cooumtput enable pin places the output in a high
impedance state which may be useful for testing or
debug. The device operates up to 250MHz and is pack-
aged in a 16 TSSOP.
FEATURES
• 4:1 single-ended multiplexer
Q
nominal
output
impedance:
7Ω
(V
DDO
=3
.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V
• Input skew: 225ps (maximum), VDD = VDDO = 3.3V
• Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V
• Operating supply modes:
V /V
DD DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK0
CLK1
CLK2
CLK3
SEL1
SEL0
OE
PIN ASSIGNMENT
Q1
1 6 VDDO
nc 2 15 nc
OE 3 14 CLK0
CLK3 4 13 nc
Q
GND 5
12 VDD
nc 6 11 nc
SEL1 7 10 CLK1
CLK2 8
9 SEL0
ICS83054I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
83054AGI
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 3, 2006


ICS83054I 데이터시트, 핀배열, 회로
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
Q Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
3
4, 8,
10, 14
5
www.DataSheet4U.com7, 9
OE
CLK3, CLK2,
CLK1, CLK0
GND
SEL1, SEL0
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power
Input
Power supply ground.
Pulldown
Clock select input. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
2, 6, 11, 13, 15 nc Unused
No connect.
12
V Power
Core and input supply pin.
DD
16
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
R
OUT
Output Impedance
Test Conditions
VDDO = 3.465V
V = 2.625V
DDO
VDDO = 1.89V
VDDO = 3.465V
VDDO = 2.625V
VDDO = 1.89V
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
SEL1
SEL0
00
Input Selected to Q
CLK0
01
CLK1
10
CLK2
11
CLK3
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
83054AGI
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 3, 2006




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ICS83054I multiplexer

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