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National Semiconductor |
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August 1998
54AC251 • 54ACT251
8-Input Multiplexer with TRI-STATE® Output
General Description
The ’AC/’ACT251 is a high-speed 8-input digital multiplexer.
It provides, in one package, the ability to select one bit of
data from up to eight sources. It can be used as universal
function generator to generate any logic function of four vari-
ables. Both true and complementary outputs are provided.
Features
n ICC reduced by 50%
n Multifunctional capability
n On-chip select logic decoding
n Inverting and noninverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT251 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC251: 5962-87692
— ’ACT251: 5962-89599
Logic Symbols
IEEE/IEC
DS100284-1
Pin Names
S0– S2
OE
I0– I7
Z
Z
Description
Select Inputs
TRI-STATE Output Enable Input
Multiplexer Inputs
TRI-STATE Multiplexer Output
Complementary TRI-STATE Multiplexer
Output
DS100284-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100284
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100284-3
Pin Assignment
for LCC
DS100284-4
Functional Description
This device is a logical implementation of a single-pole,
8-position switch with the switch position controlled by the
state of three Select inputs, S0, S1, S2. Both true and
complementary outputs are provided. The Output Enable in-
put ( OE) is active LOW. When it is activated, the logic func-
tion provided at the output is:
Z = OE • (I0 • S0 • S1 • S2 + I1• S0 • S1 • S 2 +
I2 • S0 • S 1 • S2 + I3 • S 0 • S1 • S2 +
I4 • S0 • S1 • S2 + I5 • S 0 • S1 • S2 +
I6 • S0 • S 1 • S2 + I7 • S0 • S1 • S2)
When the Output Enable is HIGH, both outputs are in the
high impedance (High Z) state. This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the TRI-STATE devices are
tied together, all but one device must be in the high imped-
ance state to avoid high currents that would exceed the
maximum ratings. The Output Enable signals should be de-
signed to ensure there is no overlap in the active-LOW por-
tion of the enable voltages.
Truth Table
Inputs
OE S2 S1
HXX
LLL
LLL
L LH
L LH
LHL
LHL
L HH
L HH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
S0
X
L
H
L
H
L
H
L
H
Outputs
ZZ
ZZ
I0 I0
I1 I1
I2 I2
I3 I3
I4 I4
I5 I5
I6 I6
I7 I7
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