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National Semiconductor |
www.DataSheet4U.com
July 1998
54AC157 • 54ACT157
Quad 2-Input Multiplexer
General Description
The ’AC/’ACT157 is a high-speed quad 2-input multiplexer.
Four bits of data from two sources can be selected using the
common Select and Enable inputs. The four outputs present
the selected data in the true (noninverted) form. The ’AC/
’ACT157 can also be used as a function generator.
Features
n ICC and IOZ reduced by 50%
n Outputs source/sink 24 mA
n ’ACT157 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC157: 5962-89539
— ’ACT157: 5962-89688
Logic Symbols
IEEE/IEC
DS100272-1
Pin Names
I0a– I0d
I1a– I1d
E
S
Za– Zd
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Description
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs
DS100272-2
Pin Assignment
for LCC
DS100272-3
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100272
DS100272-4
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Functional Description
The ’AC/’ACT157 is a quad 2-input multiplexer. It selects
four bits of data from two sources under the control of a com-
mon Select input (S). The Enable input (E) is active-LOW.
When E is HIGH, all of the outputs (Z) are forced LOW re-
gardless of all other inputs. The ’AC/’ACT157 is the logic
implementation of a 4-pole, 2-position switch where the posi-
tion of the switch is determined by the logic levels supplied to
the Select input. The logic equations for the outputs are
shown below:
Za = E • (I1a • S + I0a • S)
Zb = E • (I1b • S + I0b • S)
Zc = E • (I1c • S + I0c • S)
Zd = E • (I1d • S + I0d • S)
A common use of the ’AC/ACT157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select input. A less obvious use is as a
function generator. The ’AC/’ACT157 can generate any four
Logic Diagram
of the sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
Truth Table
Inputs
ES
HX
I0
X
LH
X
LH
X
LL
L
LL
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Outputs
I1 Z
XL
LL
HH
XL
XH
DS100272-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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