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Fairchild |
April 1988
Revised August 1999
74F258A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a common data select input. The four outputs
present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
Features
s Multiplexer expansion by tying outputs together
s Inverting 3-STATE outputs
Ordering Code:
Order Number Package Number
Package Description
74F258ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F258ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F258APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009508
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Unit Loading/Fan Out
Pin Names
S
OE
I0a–I0d
I1a–I1d
Za–Zd
Description
Common Data Select Input
3-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Inverting Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Truth Table
Output Select
Enable Input
OE S
HX
LH
LH
LL
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Data
Inputs
I0 I1
XX
XL
XH
LX
HX
Output
Z
Z
H
L
H
L
Functional Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I0x inputs are selected and when Select
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
Z n = OE • (I1n • S + I0n • S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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