74F251 반도체 회로 부품 판매점

8-Input Multiplexer with 3-STATE Outputs



Fairchild 로고
Fairchild
74F251 데이터시트, 핀배열, 회로
April 1988
Revised August 1999
74F251A
8-Input Multiplexer with 3-STATE Outputs
General Description
The 74F251A is a high-speed 8-input digital multiplexer. It
provides, in one package, the ability to select one bit of
data from up to eight sources. It can be used as a universal
function generator to generate any logic function of four
variables. Both assertion and negation outputs are pro-
vided.
Features
s Multifunctional capability
s On-chip select logic decoding
s Inverting and non-inverting 3-STATE outputs
Ordering Code:
Order Number Package Number
Package Description
74F251ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F251ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F251APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009504
www.fairchildsemi.com

74F251 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
Description
S0–S2
OE
I0–I7
Z
Z
Select Inputs
3-STATE Output Enable Input (Active LOW)
Multiplexer Inputs
3-STATE Multiplexer Output
Complementary 3-STATE Multiplexer Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
3 mA/24 mA (20 mA)
3 mA/24 mA (20 mA)
Functional Description
Truth Table
This device is a logical implementation of a single-pole, 8-
position switch with the switch position controlled by the
state of three Select inputs, S0, S1, S2. Both assertion and
negation outputs are provided. The Output Enable input
(OE) is active LOW. When it is activated, the logic function
provided at the output is:
Z = OE •(I0•S0•S1 •S2 + I1•S0•S 1•S2 +
I2•S0•S1•S2 + I3•S0•S1•S2 +
Inputs
Outputs
OE S2 S1 S0
Z
HXXXZ
Z
Z
L L L L I0 I0
L L L H I1 I1
L L H L I2 I2
I4•S0•S1•S2 + I5•S0•S1•S2 +
I6•S0•S1•S2 + I7•S0•S1•S2)
When the Output Enable is HIGH, both outputs are in the
high impedance (High Z) state. This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
L L H H I3 I3
L H L L I4 I4
L H L H I5 I5
L H H L I6 I6
together. When the outputs of the 3-STATE devices are
L H H H I7 I7
tied together, all but one device must be in the high imped- H = HIGH Voltage Level
ance state to avoid high currents that would exceed the L = LOW Voltage Level
maximum ratings. The Output Enable signals should be X = Immaterial
designed to ensure there is no overlap in the active LOW Z = High Impedance
portion of the enable voltages.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F251 multiplexer

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