|
NXP Semiconductors |
INTEGRATED CIRCUITS
DATA SHEET
OQ2535HP
SDH/SONET STM16/OC48
multiplexer
Product specification
Supersedes data of 1997 Nov 27
File under Integrated Circuits, IC19
1999 Oct 04
Philips Semiconductors
SDH/SONET STM16/OC48 multiplexer
Product specification
OQ2535HP
FEATURES
• Normal and loop (test) modes
• 3.3 V TTL compatible data inputs
• Differential Current-Mode Logic (CML) clock and data
outputs
• 5 V TTL clock output (low speed interface)
• High input sensitivity (100 mV for the high speed clock
input)
• Boundary Scan Test (BST) at low speed interface, in
accordance with “IEEE Std 1149.1-1990”
• Low power dissipation (typically 1.65 W).
GENERAL DESCRIPTION
The OQ2535HP is a 32-channel multiplexer intended for
use in STM16/OC48 applications. It combines data from a
total of 32 × 78 Mbits/s input channels onto a single
2.5 Gbits/s output channel. It features 3.3 V TTL data
inputs and a 5 V TTL clock output at the low speed
interface, and CML compatible inputs and outputs at the
high speed interface.
ORDERING INFORMATION
TYPE
NUMBER
OQ2535HP
PACKAGE
NAME
DESCRIPTION
HLQFP100 plastic heat-dissipating low profile quad flat package; 100 leads;
body 14 × 14 × 1.4 mm
VERSION
SOT470-1
BLOCK DIAGRAM
handbook, full pagewidth
78
D0 Mbits/s
to
D31
(1)
32
62
ENL
SYNSEL1
SYNSEL2
TRST
TMS
TCK
TDI
TDO
CDIV
59
58
2
5
3
7
6
13
4×
8 : 1 MUX
622 Mbits/s
4
4 : 1 MUX
2.5 Gbits/s
load
pulse
clock
SYNCHRONIZATION
OQ2535HP
78 MHz
622 MHz
DIVIDE BY 8
DIVIDE BY 4
2.5 GHz
90
91
82
83
65
66
68
69
71
72
BAND GAP
REFERENCE 1
61 38
10
BAND GAP
REFERENCE 2
78 16
74
75
14, 37,
12, 39,
(2)
63, 85, 86 87, 88 60
54
REFC1 REFC2 BGCAP1
BGCAP2 VCC(T) VDD
VEE
(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100.
31
VCC GND
Fig.1 Block diagram.
DOUT
DOUTQ
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
CIN
CINQ
DIOA
DIOC
MGK351
1999 Oct 04
2
|