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STMicroelectronics |
® 74VHC257
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
s HIGH SPEED: tPD = 3.7 ns (TYP.) at VCC = 5V
s LOWPOWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257
s IMPROVED LATCH-UP IMMUNITY
s LOWNOISE VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHC257 is an advanced high-speed
CMOS QUAD 2 CHANNEL MULTIPLEXER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
It is composed of four independent 2 channel
multiplexers with common SELECT and ENABLE
INPUT.
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC257M
74VHC257T
The 74VHC257 is a non inverting multiplexer.
When the ENABLE INPUT is held ”High”, all
outputs become high impedance state. If
SELECT INPUT is held ”Low”, ”A” data is
selected, when SELECT INPUT is ”High”, ”B”
data is chosen.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/9
74VHC257
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 14, 11
3, 6, 13, 10
4, 7, 12, 9
15
8
16
S YM BO L
SELECT
1A to 4A
1B to 4B
1Y to 4Y
OE
GND
VCC
NAME AND FUNCTION
Common Data Select Input
Data Input From Source A
Data Inputs from Source B
3 State Multiplexer Outputs
3 State Output Enable
Inputs (Active LOW)
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
OE SELE CT
HX
LL
LL
LH
LH
X = DON’T CARE Z = HIGH IMPEDANCE
INPUT S
LOGIC DIAGRAM
A
X
L
H
X
X
OU T PU T S
BY
XZ
XL
XH
LL
HH
Thislogic diagram has notbe used to estimate propagation delays
2/9
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