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Fairchild Semiconductor |
June 1993
Revised March 1999
74LVX138
Low Voltage 1-of-8 Decoder/Demultiplexer
General Description
The LVX138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three LVX138 devices or a 1-of-32 decoder using four
LVX138 devices and one inverter.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX138M
74LVX138SJ
M16A
M16D
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX138MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A2
E1– E2
E3
O0–O7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 1999 Fairchild Semiconductor Corporation DS011615.prf
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Functional Description
The LVX138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and,
when enabled, provides eight mutually exclusive active-
LOW outputs (O0–O7). The LVX138 features three Enable
inputs, two active-LOW (E1, E2) and one active-HIGH (E3).
All outputs will be HIGH unless E1 and E2 are LOW and E3
is HIGH.
The LVX138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data
input and the other Enable inputs as strobes. The Enable
inputs which are not used must be permanently tied to their
appropriate active-HIGH or active-LOW state.
Truth Table
Inputs
Outputs
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
HX X X X X HHHHHHHH
X HX X X X HHHHHHHH
XX L XXXHHHHHHHH
L LH L LL LHHHHHHH
L LHHL LHLHHHHHH
L LH LHLHHLHHHHH
L LHHHLHHH LHHHH
L L H L LHHHHH L HHH
L LHHLHHHHHHLHH
L LH LHHHHHHHH LH
L LHHHHHHHHHHHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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