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74LS253 반도체 회로 부품 판매점

3-STATE Data Selector/Multiplexer



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LS253 데이터시트, 핀배열, 회로
August 1986
Revised March 2000
DM74LS253
3-STATE Data Selector/Multiplexer
General Description
Each of these Schottky-clamped data selectors/multiplex-
ers contains inverters and drivers to supply fully comple-
mentary, on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are pro-
vided for each of the two four-line sections.
The 3-STATE outputs can interface directly with data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high impedance state), the low
impedance of the single enabled output will drive the bus
line to a HIGH or LOW logic level.
Features
s 3-STATE version of DM74LS153 with same pinout
s Schottky-diode-clamped transistors
s Permit multiplexing from N-lines to one line
s Performs parallel-to-serial conversion
s Strobe/output control
s High fanout totem-pole outputs
s Typical propagation delay
Data to output 12 ns
Select to output 21 ns
s Typical power dissipation 35 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS253M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS253N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Select
Data Inputs
Output
Inputs
Control
B A C0 C1 C2 C3 G
X X X X XX
H
L L L X XX
L
L L H X XX
L
L H X L XX
L
L H X H XX
L
H L X X LX
L
H L X X HX
L
H H X X XL
L
H H X X XH
L
Address Inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don't Care
Z = High Impedance (OFF)
Output
Y
Z
L
H
L
H
L
H
L
H
© 2000 Fairchild Semiconductor Corporation DS006416
www.fairchildsemi.com


74LS253 데이터시트, 핀배열, 회로
Logic Diagram
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74LS253 multiplexer

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