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Fairchild Semiconductor |
November 1988
Revised August 2000
74AC138 • 74ACT138
1-of-8 Decoder/Demultiplexer
General Description
The AC/ACT138 is a high-speed 1-of-8 decoder/demulti-
plexer. This device is ideally suited for high-speed bipolar
memory chip select address decoding. The multiple input
enables allow parallel expansion to a 1-of-24 decoder
using just three AC/ACT138 devices or a 1-of-32 decoder
using four AC/ACT138 devices and one inverter.
Features
s ICC reduced by 50%
s Demultiplexing capability
s Multiple input enable for easy expansion
s Active LOW mutually exclusive outputs
s Outputs source/sink 24 mA
s ACT138 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC138SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74AC138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC138MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC138PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT138SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74ACT138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT138PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbols
Pin Descriptions
Pin Names
A0–A2
E1–E2
E3
O0–O7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS009925
IEEE/IEC
www.fairchildsemi.com
Truth Table
Inputs
Outputs
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
HX X X X X HHHHHHHH
X HX X X X HHHHHHHH
XX L XXXHHHHHHHH
L LH L L L LHHHHHHH
L LHHL LHLHHHHHH
L LH LHLHHLHHHHH
L LHHHLHHH LHHHH
L LH L LHHHHHLHHH
L LHHLHHHHHHLHH
L LH LHHHHHHHH LH
L LHHHHHHHHHHHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The AC/ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and,
when enabled, provides eight mutually exclusive active-
LOW outputs (O0–O7). The AC/ACT138 features three
Enable inputs, two active-LOW (E1, E2) and one active-
HIGH (E3). All outputs will be HIGH unless E1 and E2 are
LOW and E3 is HIGH. This multiple enable function allows
easy parallel expansion of the device to a 1-of-32 (5 lines
to 32 lines) decoder with just four AC/ACT138 devices and
one inverter (see Figure 1). The AC/ACT138 can be used
as an 8-output demultiplexer by using one of the active
LOW Enable inputs as the data input and the other Enable
inputs as strobes. The Enable inputs which are not used
must be permanently tied to their appropriate active-HIGH
or active-LOW state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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FIGURE 1. Expansion to 1-of-32 Decoding
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