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Fairchild Semiconductor |
April 1988
Revised March 1999
74F151A
8-Input Multiplexer
General Description
The F151A is a high-speed 8-input digital multiplexer. It
provides in one package the ability to select one line of
data from up to eight sources. The F151A can be used as a
universal function generator to generate any logic function
of four variables. Both assertion and negation outputs are
provided.
Ordering Code:
Order Number Package Number
Package Description
74F151ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F151ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F151APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
I0–I7
S0–S2
E
Data Inputs
Select Inputs
Enable Input (Active LOW)
1.0/1.0
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Z Data Output
50/33.3 −1 mA/20 mA
Z
Inverted Data Output
50/33.3 −1 mA/20 mA
© 1999 Fairchild Semiconductor Corporation DS009481.prf
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Functional Description
The F151A is a logic implementation of a single pole, 8-
position switch with the switch position controlled by the
state of three Select inputs, S0, S1, S2. Both assertion and
negation outputs are provided. The Enable input (E) is
active LOW. When it is not activated, the negation output is
HIGH and the assertion output is LOW regardless of all
other inputs. The logic function provided at the output is:
Z = E • (I0 S2 S1 S0 + I1 S2 S1 S0 + I2 S2 S1 S0 +
I3 S2 S1 S0 + I4 S2 S1 S0 + I5 S2 S1 S0 +
I6 S2 S1 S0 + I7 S2 S1 S0)
The F151A provides the ability, in one package, to select
from eight sources of data or control information. By proper
manipulation of the inputs, the F151A can provide any logic
function of four variables and its negation.
Logic Diagram
Truth Table
Inputs
E S2 S1
HX
X
LL
L
LL
L
LL H
LL
LH
LH
LH
LH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
H
L
L
H
H
S0
X
L
H
L
H
L
H
L
H
Outputs
ZZ
HL
I0 I0
I1 I1
I2 I2
I3 I3
I4 I4
I5 I5
I6 I6
I7 I7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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