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74F138PC 반도체 회로 부품 판매점

1-of-8 Decoder/Demultiplexer



Fairchild Semiconductor 로고
Fairchild Semiconductor
74F138PC 데이터시트, 핀배열, 회로
April 1988
Revised July 1999
74F138
1-of-8 Decoder/Demultiplexer
General Description
The F138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three F138 devices or a 1-of-32 decoder using four F138
devices and one inverter.
Features
s Demultiplexing capability
s Multiple input enable for easy expansion
s Active LOW mutually exclusive outputs
Ordering Code:
Order Number Package Number
Package Description
74F138SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F138PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009478
www.fairchildsemi.com


74F138PC 데이터시트, 핀배열, 회로
Unit Loading/Fan Out
Pin Names
A0–A2
E1, E2
E3
O0–O7
Description
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
1 mA/20 mA
Truth Table
Inputs
Outputs
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
HXXXXXHH H HHHHH
XHXXXXHH H HHHHH
XX LXXXHH H HHHHH
L LH L L L LH H HHHHH
L LHH L LH L H HHHHH
L LH LH LHH L HHHHH
L LHHH LHH H LHHHH
L LH L LHHH H HLHHH
L LHH LHHH H HHLHH
L LH LHHHH H HHHLH
L LHHHHHH H HHHHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The F138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and,
when enabled, provides eight mutually exclusive active
LOW outputs (O0–O7). The F138 features three Enable
inputs, two active LOW (E1, E2) and one active HIGH (E3).
All outputs will be HIGH unless E1 and E2 are LOW and E3
is HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four F138 devices and one inverter (See
Figure 1). The F138 can be used as an 8-output demulti-
plexer by using one of the active LOW Enable inputs as the
data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active HIGH or active LOW state.
www.fairchildsemi.com
FIGURE 1. Expansion to 1-of-32 Decoding
2




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74F138PC multiplexer

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