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74ACT253 반도체 회로 부품 판매점

Dual 4-Input Multiplexer with TRI-STATE Outputs



National Semiconductor 로고
National Semiconductor
74ACT253 데이터시트, 핀배열, 회로
August 1998
54AC253 54ACT253
Dual 4-Input Multiplexer with TRI-STATE® Outputs
General Description
The ’AC/’ACT253 is a dual 4-input multiplexer with
TRI-STATE outputs. It can select two bits of data from four
sources using common select inputs. The outputs may be in-
dividually switched to a high impedance state with a HIGH
on the respective Output Enable (OE) inputs, allowing the
outputs to interface directly with bus oriented systems.
n Multifunction capability
n Noninverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT253 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC253: 5962-87693
— ’ACT253: 5962-87761
Features
n ICC and IOZ reduced by 50%
Logic Diagrams
IEEE/IEC
DS100285-1
Pin Names
I0a– I3a
I0b– I3b
S0, S1
OEa
OEb
Za, Zb
Description
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
TRI-STATE Outputs
DS100285-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100285
www.national.com


74ACT253 데이터시트, 핀배열, 회로
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100285-3
DS100285-4
Functional Description
The ’AC/’ACT253 contains two identical 4-input multiplexers
with TRI-STATE outputs. They select two bits from four
sources selected by common Select inputs (S0, S1). The
4-input multiplexers have individual Output Enable (OEa,
OEb) inputs which, when HIGH, force the outputs to a high
impedance (High Z) state. This device is the logic implemen-
tation of a 2-pole, 4-position switch, where the position of the
switch is determined by the logic levels supplied to the two
select inputs. The logic equations for the outputs are shown:
Za = OEa (I0a S1 S0 + I1a S1 S0 +
Truth Table
I2a S1 S0 + I3a S1 S0)
Zb = OEb (I0b S1 S0 + I1b S1 S0 +
I2b S1 S0 + I3b S1 S0)
If the outputs of TRI-STATE devices are tied together, all but
one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings. De-
signers should ensure that Output Enable signals to
TRI-STATE devices whose outputs are tied together are de-
signed so that there is no overlap.
Select
Inputs
S0 S1
XX
LL
LL
HL
HL
LH
LH
HH
HH
Data Inputs
I0 I1 I2 I3
XXXX
LXXX
HXXX
XLXX
XHXX
XXLX
XXHX
XXXL
XXXH
Address Inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Output
Enable
OE
H
L
L
L
L
L
L
L
L
Outputs
Z
Z
L
H
L
H
L
H
L
H
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74ACT253 multiplexer

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