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Analog Switch and Multiplexer Applications



Intersil Corporation 로고
Intersil Corporation
AN1034 데이터시트, 핀배열, 회로
AN101
An Introduction to FETs
Introduction
The basic principle of the field-effect transistor (FET) has
been known since J. E. Lilienfeld’s patent of 1925. The
theoretical description of a FET made by Shockley in
1952 paved the way for development of a classic electron-
ic device which provides the designer the means to ac-
complish nearly every circuit function. At one time, the
field-effect transistor was known as a “unipolar” transis-
tor. The term refers to the fact that current is transported
by carriers of one polarity (majority), whereas in the con-
ventional bipolar transistor carriers of both polarities
(majority and minority) are involved.
This Application Note provides an insight into the nature of
the FET, and touches briefly on its basic characteristics, ter-
minology, parameters, and typical applications.
The following list of FET applications indicates the ver-
satility of the FET family:
Amplifiers
S Small Signal
S Low Distortion
S High Gain
S Low Noise
S Selectivity
S DC
Switches
S Chopper-Type
S Analog Gate
S Communicator
Protection Diodes
S Low-leakage
S High-Frequency
Current Limiters
Voltage-Controlled Resistors
Mixers
Oscillators
The family tree of FET devices (Figure 1) may be divided
into two main branches, Junction FETs (JFETs) and Insu-
lated Gate FETs (or MOSFETs, metal-oxide- semicon-
ductor field-effect transistors). Junction FETs are in-
herently depletion-mode devices, and are available in
both n- and p-channel configurations. MOSFETs are
available in both enhancement and depletion modes, and
also exist as both n- and p-channel devices. The two main
FET groups depend on different phenomena for their op-
eration, and will be discussed separately.
Junction FETs
In its most elementary form, this transistor consists of a
piece of high-resistivity semiconductor material (usually
silicon) which constitutes a channel for the majority carri-
er flow. The magnitude of this current is controlled by a
voltage applied to a gate, which is a reverse-biased pn
junction formed along the channel. Implicit in this de-
scription is the fundamental difference between JFET and
bipolar devices: when the JFET junction is reverse-biased
the gate current is practically zero, whereas the base cur-
rent of the bipolar transistor is always some value greater
than zero. The JFET is a high-input resistance device,
while the input resistance of the bipolar transistor is com-
paratively low. If the channel is doped with a donor impu-
rity, n-type material is formed and the channel current
will consist of electrons. If the channel is doped with an
acceptor impurity, p-type material will be formed and the
channel current will consist of holes. N-channel devices
have greater conductivity than p-channel types, since
electrons have higher mobility than do holes; thus n-chan-
nel JFETs are approximately twice as efficient conductors
compared to their p-channel counterparts.
FETs
Junction
MOS
Depletion
np
Enhancement
Not Possible
Depletion
np
Figure 1. FET Family Tree
Enhancement
np
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70594.
Siliconix
10-Mar-97
1


AN1034 데이터시트, 핀배열, 회로
AN101
In addition to the channel material, a JFET contains two
ohmic (non-rectifying) contacts: the source and the drain.
These are shown in Figure 2. Since a symmetrical geome-
try is shown in the idealized JFET chip, it is immaterial
which contact is called the source and which is called the
drain; the JFET will conduct current equally well in either
direction and the source and drain leads are usually inter-
changeable.
layer as VDS increases. The curve approaches the level of
the limiting current IDSS when ID begins to be pinched off.
The physical meaning of this term leads to one definition
of pinch-off voltage, VP, which is the value of VDS at
which the maximum IDSS flows.
VDS < VP
N-Source
N-Drain
Channel
SD
P
N
Depletion
Layer
N-Channel
P-Gate
Final form taken by FET with n-type channel embedded in p-type
substrate.
Figure 2. Idealized Structure of An N-Channel
Junction FET
P
G
3a) N-Channel FET Working in the Ohmic Region (VGS =
0 V) (Depletion Shown Only in Channel Region)
(For certain JFET applications, such as high-frequency
amplifiers, an asymmetrical geometry is preferred for
lower capacitance and improved frequency response. In
these cases, the source and drain leads should not be inter-
changed.)
Figure 3 shows how the JFET functions. If the gate is con-
nected to the source, then the applied voltage (VDS) will
appear between the gate and the drain. Since the pn junc-
tion is reverse-biased, little current will flow in the gate
connection. The potential gradient established will form
a depletion layer, where almost all the electrons present
in the n-type channel will be swept away. The most de-
pleted portion is in the high field between the gate and the
drain, and the least-depleted area is between the gate and
the source. Because the flow of current along the channel
from the (positive) drain to the (negative) source is really
a flow of free electrons from source to drain in the n-type
silicon, the magnitude of this current will fall as more sili-
con becomes depleted of free electrons. There is a limit
to the drain current (ID) which increased VDS can drive
through the channel. This limiting current is known as
IDSS (Drain-to-Source current with the gate shorted to the
source). Figure b shows the almost complete depletion of
the channel under these conditions.
Figure 3c shows the output characteristics of an n-channel
JFET with the gate short-circuited to the source. The
initial rise in ID is related to the buildup of the depletion
2
VDS > VP
SD
P
N
P
G
Depletion
Layer
3b) N-Channel FET Working in the Current Saturation
Region (VGS = 0)
IDSS
Saturation Region
Current
ID
Ohmic
Region
VGS = 0 V
VP VDS
3c) Idealized Output Characteristic for VGS = 0
Figure 3.
Siliconix
10-Mar-97




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