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74LVC157A-Q100 반도체 회로 부품 판매점

Quad 2-input multiplexer



NXP Semiconductors 로고
NXP Semiconductors
74LVC157A-Q100 데이터시트, 핀배열, 회로
74LVC157A-Q100
Quad 2-input multiplexer
Rev. 2 — 2 May 2013
Product data sheet
1. General description
The 74LVC157A-Q100 is a quad 2-input multiplexer which select four bits of data from two
sources under the control of a common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable input (E) is active LOW. When
pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other
input conditions. Moving the data from two groups of registers to four common output
buses is a common use of the 74LVC157A-Q100. The state of the common data select
input (S) determines the particular register from which the data comes. It can also be used
as function generator.
It is useful for implementing highly irregular logic by generating any 4 of the 16 different
functions of two variables with one variable common.
The device is the logic implementation of a 4-pole, 2-position switch, where the position of
the switch is determined by the logic levels applied to pin S.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options


74LVC157A-Q100 데이터시트, 핀배열, 회로
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC157AD-Q100 40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC157ADB-Q100 40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LVC157APW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74LVC157ABQ-Q100 40 C to +125 C
DHVQFN16 plastic dual In-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5 3.5 0.85 mm
SOT763-1
4. Functional diagram
2 3 5 6 11 10 14 13
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
1S
15 E
1Y 2Y 3Y 4Y
47
Fig 1. Logic symbol
9 12
mna481
1
G1
15 EN
2 1 MUX
31
5
6
11
10
14
13
4
7
9
12
mna482
Fig 2. IEC logic symbol
Fig 3. Functional diagram
74LVC157A_Q100
Product data sheet
2 1I0
3 1I1
5 2I0
6 2I1
11 3I0
10 3I1
14 4I0
13 4I1
SELECTOR
S
1
1Y 4
2Y 7
MULTIPLEXER
OUTPUTS
3Y 9
4Y 12
E
15 mna483
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
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74LVC157A-Q100 multiplexer

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Quad 2-input multiplexer - NXP Semiconductors