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PDF NVD4856N Data sheet ( Hoja de datos )
| Número de pieza | NVD4856N | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NTD4856N, NVD4856N
Power MOSFET
25 V, 89 A, Single N−Channel, DPAK/IPAK
Features
• Trench Technology
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Applications
• VCORE Applications
• DC−DC Converters
• Low Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJA
(Note 1)
Power Dissipation
RqJA (Note 1)
Continuous Drain
Current RqJA
(Note 2)
Power Dissipation
RqJA (Note 2)
Steady
State
Continuous Drain
Current RqJC
(Note 1)
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
tp=10ms
TA = 25°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
TC = 25°C
TA = 25°C
VDSS
VGS
ID
PD
ID
PD
ID
PD
IDM
25
±20
16.8
13.0
2.14
13.3
10.3
1.33
89
69
60
179
V
V
A
W
A
W
A
W
A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
IDmaxPkg
TJ,
TSTG
IS
dV/dt
45
−55 to
+175
50
6
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 19 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
TL
180.5 mJ
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
http://onsemi.com
V(BR)DSS
25 V
RDS(ON) MAX
4.7 mW @ 10 V
6.8 mW @ 4.5 V
D
ID MAX
89 A
N−Channel
G
S
4
4
4
12
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
1 23
1
2
3
3 IPAK
CASE 369AC
(Straight Lead)
IPAK
CASE 369D
(Straight Lead
DPAK) STYLE 2
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS 4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
A = Assembly Location*
Y = Year
WW = Work Week
4856N = Device Code
G = Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 3
1
Publication Order Number:
NTD4856N/D
1 page  
NTD4856N, NVD4856N
TYPICAL PERFORMANCE CURVES
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
0
VGS = 0 V
Ciss TJ = 25°C
Coss
Crss
5 10 15 20
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
25
Figure 7. Capacitance Variation
1000
VDD = 15 V
ID = 30 A
VGS = 11.5 V
100
10
td(off)
tf
tr
td(on)
1
1
1000
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
100
10 ms
10
VGS = 20 V
SINGLE PULSE
1 TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
0.1
0.1
PACKAGE LIMIT
1
10
100 ms
1 ms
10 ms
dc
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
12
10 QT
8
6
4 Q1
Q2
VGS
2 ID = 30 A
TJ = 25°C
0
0 4 8 12 16 20 24 28 32 36 40
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
VGS = 0 V
25 TJ = 25°C
20
15
10
5
0
0.2 0.4
0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
200
180 ID = 19 A
160
140
120
100
80
60
40
20
0
25 50
75
100
125 150
175
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
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