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Pan Jit International |
PJ2306
30V N-Channel Enhancement Mode MOSFET - ESD Protected
FEATURES
• RDS(ON), VGS@10V,IDS@3.2A=65mΩ
• RDS(ON), VGS@4.5V,IDS@2.8A=85mΩ
• Advanced Trench Process Technology
• High Density Cell Design For Ultra Low On-Resistance
• Very Low Leakage Current In Off Condition
• Specially Designed for Load Switch, PWM Applications
• ESD Protected
• Component are in compliance with EU RoHS 2002/95/EC directives
MECHANICALDATA
• Case: SOT-23 Package
• Terminals : Solderable per MIL-STD-750,Method 2026
• Marking : 06
D
3
12
GS
Maximum RATINGS and Thermal Characteristics (TA=25OC unless otherwise noted )
PA RA ME TE R
S ym b o l
Limit
Drain-Source Voltage
V DS
30
Gate-Source Voltage
V GS
+20
Continuous Drain Current
ID 3 .2
Pulsed Drain Current 1)
Maxi mum P ower Di ssi pati on
TA = 2 5 OC
TA = 7 5 OC
Op e ra ti ng J unc ti o n a nd S to ra g e Te m p e ra ture Ra ng e
IDM
PD
T J , T S TG
16
1.25
0.75
-55 to + 150
Junction-to Ambient Thermal Resistance(PCB mounted)2
R θJ A
100
Note: 1. Maximum DC current limited by the package
2. Surface mounted on FR4 board, t < 5 sec
Uni ts
V
V
A
A
W
OC
OC /W
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PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE
June 03, 2010-REV.00
PAGE . 1
PJ2306
ELECTRICALCHARACTERISTICS
Parameter
Static
Drain-Source Breakdown
Voltage
Gate Threshold Voltage
Drain-Source On-State
Re s i s ta nc e
Zero Gate Voltage Drain
C urre nt
Gate Body Leakage
Forward Transconductance
Diode Forward Voltage
Dynamic
To t a l G a t e C ha r g e
S ymbol
Te s t C o nd i ti o n
B V DSS
V GS(th)
R D S (o n)
R D S (o n)
ID S S
IGS S
g fS
V SD
V GS=0 V, ID=2 5 0 uA
V DS=V GS, ID=2 5 0 uA
VGS=4.5V, I D=2.8A
VGS=10V, I D=3.2A
VDS=24V, VGS=0V
VGS=+16V, VDS=0V
V DS=4 .5 V, ID=2 .8 A
IS=2.8A , V GS=0V
V DS = 1 5 V, ID= 3 . 2 A , VGS=5V
Qg
Gate-Source C harge
Gate-Grain Charge
Turn-On D e la y Ti me
Ri s e Ti me
Turn-Off D e la y Ti me
F a ll Ti m e
Inp ut C a p a c i ta nc e
Output Capacitance
Re ve r s e Tr a ns f e r
C a p a c i ta nce
Qgs
Qgd
t d (o n)
tr
t d (o ff)
tf
C iss
C oss
C rss
V DS=1 5 V, ID=3 .2 A
VGS=10V
VDD=15V , RL=15Ω
ID=1A , VGEN=10V
RG=6Ω
V DS=15 V, V GS=0V
f=1.0MHZ
NOTE : Plus Test : Pluse Width < 300us, Duty Cycle < 2%.
Mi n.
30
1
3
Typ .
Max. Uni ts
72
55
0.88
2.5
85
65
1
+10
1.2
V
V
mΩ
uA
uA
S
V
2.8
5.0
0.5
1.1
8.6
12.8
18.6
1.9
270
45
30
3.5
6.5
11.2
16.8
26
2.6
nC
ns
pF
Switching
Test Circuit
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VIN
RG
VDD
RL
VOUT
Gate Charge
Test Circuit
VGS
1mA
RG
VDD
RL
June 03, 2010-REV.00
PAGE . 2
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