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PDF ZL1505 Data sheet ( Hoja de datos )
| Número de pieza | ZL1505 | |
| Descripción | Synchronous Step-Down MOSFET Drivers | |
| Fabricantes | intersil | |
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Synchronous Step-Down MOSFET Drivers
ZL1505
The ZL1505 is an integrated high-speed, high-current
N-channel MOSFET driver for synchronous step-down
DC-DC conversion applications. When used with Zilker
Labs Digital-DC™ PWM controllers, the ZL1505 enables
dynamically adaptive dead-time control that optimizes
efficiency under all operating conditions. A dual input
PWM configuration enables this efficiency optimization
while minimizing complexity within the driver.
Operating from a 4.5V to 7.5V input, the ZL1505
combines a 5A, 0.5W low-side driver and a 3A, 0.8W
high-side driver to support high step-down buck
applications. A unique adjustable gate drive current
scheme allows the user to adjust the drive current on
both drivers to optimize performance for a wide rage of
input/output voltages, load currents, power MOSFETs
and switching frequencies up to 1.4MHz. An integrated
30V bootstrap Schottky diode is used to charge the
external bootstrap capacitor. An internal watchdog circuit
prevents excessive shoot-through currents and protects
the external MOSFET switches.
The ZL1505 is specified over a wide -40°C to +125°C
junction temperature range and is available in an
exposed pad DFN-10 package.
Features
• High-speed, high-current drivers for synchronous
N-channel MOSFETs
• Adaptive dead-time control optimizes efficiency
when used with Digital-DC controllers
• Integrated 30V bootstrap Schottky diode
• Capable of driving 40A per phase
• Supports switching frequency up to 1.4MHz
- >4A source, >5A sink low-side driver
- >3A source/sink high-side driver
- <10ns rise/fall times, low propagation delay
• Adjustable gate drive strength optimizes efficiency
for different VIN, VOUT, IOUT, FSW and MOSFET
combinations
• Internal non-overlap watchdog prevents
shoot-through currents
Applications*(see page 12)
• High efficiency, high-current DC/DC buck converters
with digital control and PMBus™
• Multi-phase digital DC/DC converters with phase
adding/dropping
• Power train modules
• Synchronous rectification for secondary side isolated
power converters
Related Literature*(see page 12)
• FN6846 ZL2004 Data Sheet
VDD
PWMH
PWML
HSEL
Level
shift
Shoot-
through
Protection
VDD
ZL1505
GND LSEL
FIGURE 1. ZL1505 BLOCK DIAGRAM
BST
GH
SW
GL
December 4, 2009
FN6845.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ZL1505
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Electrical Specifications
VDD = 6.5V, TJ = -40°C to +125°C unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER
CONDITIONS
MIN
MAX
(Note 9) TYP (Note 9) UNIT
THERMAL PROTECTION
Thermal trip point
– 150 –
°C
Thermal reset point
– 134 –
°C
UPPER GATE DRIVER CHARACTERISTICS
Driver Voltage (VBST – VSW)
High-side Driver Peak Gate Drive
Current (Pull-up)
(VGH – VSW) = 2.5V
HSEL connected
to BST
–6
2.0 3.2
–
–
V
A
HSEL connected
to SW
1.0 1.7
-
A
High-side Driver Peak Gate Drive
Current (Pull-down)
(VGH – VSW) = 2.5V
HSEL connected
to BST
2.0 3.2
–
A
HSEL connected
to SW
1.0 1.6
-
A
High-side Driver Pull-up Resistance
(VBST – VGH) = 50mV
HSEL connected
to BST
– 0.7 0.9
Ω
HSEL connected
to SW
- 0.9 1.2 Ω
High-side Driver Pull-down Resistance (VGH – VSW) = 50mV
HSEL connected
to BST
– 0.8 1.1
Ω
HSEL connected
to SW
1.1 1.5
Ω
LOWER GATE DRIVER CHARACTERISTICS
Driver voltage (VDD)
Low-side Driver Peak Gate Drive Current (VGL - VGNG) = 2.5V
(Pull-up)
LSEL connected
to VDD
- 6.5
3.0 4.5
-
–
V
A
LSEL connected
to GND
1.5 2.4
-
A
Low-side Driver Peak Gate Drive Current (VGL – VGND) = 2.5V
(Pull-down)
LSEL connected
to VDD
3.5 5.4
–
A
LSEL connected
to GND
1.8 2.8
-
A
Low-side Driver Pull-up Resistance
(VDD - VGL) = 50mV
LSEL connected
to VDD
– 0.7 0.9
Ω
LSEL connected
to GND
- 1.0 1.3 Ω
Low-side Driver Pull-down Resistance (VGL – GND) = 50mV
LSEL connected
to VDD
– 0.5 0.7
Ω
LSEL connected
to GND
- 0.7 1.0 Ω
SWITCHING CHARACTERISTICS
GH rise time, tRH
CGH = 3nF
HSEL connected
to BST
– 5.3 8.5 ns
HSEL connected
to SW
-
10.5 16.5
ns
5 FN6845.1
December 4, 2009
5 Page 
ZL1505
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ZL1505 Overview
Theory of Operation
The ZL1505 is a synchronous N-channel MOSFET driver
that is intended for use with Zilker Labs Digital-DC PWM
controllers to enable a high-efficiency DC/DC conversion
scheme. The patented Digital-DC control scheme utilizes
a closed-loop algorithm to optimize the dead-time
applied between the gate drive signals for the high-side
and low-side MOSFETs. By monitoring the duty cycle of
the resulting DC/DC converter circuit, this dynamic
routine continuously varies the MOSFET dead times to
optimize conversion efficiency in response to varying
circuit conditions. The ZL1505’s dual PWM input
configuration enables this optimization scheme to be
applied while minimizing the complexity within the driver
device. Please refer to the ZL2004 data sheet for details
on the dynamic dead-time optimization routine.
The ZL1505 integrates two powerful gate drivers that
have been optimized for step-down DC/DC conversion
circuit configurations whose output current can exceed
40A per phase. The ZL1505 also integrates a 30V
bootstrap Schottky diode to minimize the external
components and provide a high drive voltage to the
high-side driver device.
condition ceases, allowing normal switching operation to
continue.
Start-up Requirements
During power-up, the ZL1505 maintains both GH and GL
outputs in the LOW state while the VIN voltage is
ramping up. Once the VDD supply is within specification,
the GH and GL pins may be operated using the PWMH
and PWML logic inputs respectively.
In the case where the PWM controller is powered from a
supply other than the ZL1505’s VDD supply, and the PWM
controller is powered up first, the PWM controller gate
outputs should be kept in low or in high-impedance state
until the VDD supply is within specification. Additionally, if
the ZL1505 begins its power-down sequence prior to the
PWM controller then the PWM controller gate outputs
should be set in low or in high-impedance state before
the VDD voltage supply drops below its specified range.
Thermal protection
When the junction temperature exceeds +150°C the
high-side driver output GH is forced to logic low state.
The driver output is allowed to switch logic states again
once the junction temperature drops below +134°C.
Variable Gate Drive Current
The ZL1505 incorporates an innovative variable drive
current scheme that enables the user to optimize the
gate drive current levels to the requirements of the
external MOSFETs used over a wide range of operating
frequencies. Each of the gate drivers incorporates a logic
input (HSEL and LSEL) that allows the user to select the
gate drive strength to 50% or 100% of the total rated
drive current.
With the HSEL pin connected to the BST pin, the
high-side driver can deliver the full rated gate drive
current; with the HSEL pin connected to the SW pin, the
output current will be limited to 50% of the full rated
output capability. With the LSEL pin connected to VDD,
the low-side driver can deliver the full rated gate drive
current; with the LSEL pin connected to GND, the output
current will be limited to 50% of the full rated output
capability. Using HSEL and LSEL, the ZL1505 can be used
across a wide range of applications using only a simple
PCB layout change.
Also, the VDD pin is the gate drive bias supply for the
external MOSFETs. VDD can be used to vary the gate
drive strength as shown for the low-side driver in
Figures 9 thru 12 and for the high-side driver in
Figures 17 thru 20.
Overlap Protection Circuit
The ZL1505 includes an internal watchdog circuit that
prevents excessive shoot-through current from occurring
in the unlikely event that the PWM converter places both
switches in the ON position. If the overlap time between
the PWMH and PWML pulses exceeds 30ns, the PWMH
signal will be forced to the LOW state until the overlap
11 FN6845.1
December 4, 2009
11 Page | ||
| Páginas | Total 13 Páginas | |
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