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MOSFET ( Transistor )



Fairchild Semiconductor 로고
Fairchild Semiconductor
FDN361BN 데이터시트, 핀배열, 회로
October 2005
FDN361BN
30V N-Channel, Logic Level, PowerTrench® MOSFET
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones,
PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are
needed in a very small outline surface mount package.
Features
1.8 A, 30 V.
RDS(ON) = 110 mΩ @ VGS = 10 V
RDS(ON) = 160 mΩ @ VGS = 4.5 V
Low gate charge
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities
High performance trench technology for extremely
low RDS(ON)
DD
SuperSOTTM-3
G
www.DataSheet4U.com
S
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1a)
PD
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
361B
FDN361BN
7’’
©2005 Fairchild Semiconductor Corporation
FDN361BN Rev A(W)
GS
Ratings
30
± 20
1.4
10
0.5
0.46
–55 to +150
250
75
Units
V
V
A
W
°C
°C/W
Tape width
8mm
Quantity
3000 units
www.fairchildsemi.com


FDN361BN 데이터시트, 핀배열, 회로
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSS Gate–Body Leakage
On Characteristics (Note 2)
VGS(th)
Gate Threshold Voltage
RDS(on)
Static Drain–Source
On–Resistance
ID(on)
On–State Drain Current
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
RG Gate Resistance
Switching Characteristics
td(on) Turn–On Delay Time
tr Turn–On Rise Time
td(off) Turn–Off Delay Time
tf Turn–Off Fall Time
Qg Total Gate Charge
Qgs Gate–Source Charge
Qgd Gate–Drain Charge
(Note 2)
Drain–Source Diode Characteristics
VSD Drain–Source Diode Forward
Voltage
trr Diode Reverse Recovery Time
Qrr Diode Reverse Recovery Charge
VGS = 0 V,
ID = 250 μA
ID = 250 μA,Referenced to 25°C
VDS = 24 V,
VGS = 0 V
VDS = 24 V, VGS = 0 V, TJ = 55°C
VGS = ±20 V, VDS = 0 V
VDS = VGS,
ID = 250 μA
VGS = 10 V,
ID = 1.4 A
VGS = 4.5 V, ID = 1.2 A
VGS = 10 V, ID = 1.4 A, TJ = 125°C
VGS = 4.5 V, VDS = 5 V
VDS = 5 V,
ID = 1.4 A
VDS = 15 V,
f = 1.0 MHz
V GS = 0 V,
VGS = 15 mV, f = 1.0 MHz
VDD = 15 V,
VGS = 10 V,
ID = 1 A,
RGEN = 6 Ω
VDS = 15 V,
VGS = 4.5 V
ID = 1.4 A,
VGS = 0 V, IS = 0.42 A (Note 2)
IF = 1.4 A, diF/dt = 100 A/µs
30
1
3.5
V
26 mV/°C
1
10
±100
μA
μA
nA
2.1 3
92 110
120 160
114 150
4
V
mΩ
A
S
145 193
35 47
15 23
1.6
pF
pF
pF
Ω
36
8 16
16 29
24
1.3 1.8
0.5
0.5
ns
ns
ns
ns
nC
nC
nC
0.8 1.2
11 22
4
V
nS
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 250°C/W when mounted on a
0.02 in2 pad of 2 oz. copper.
b) 270°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width 300 μs, Duty Cycle 2.0%
FDN361BN Rev A(W)
www.fairchildsemi.com




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