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NIF9N05CL 반도체 회로 부품 판매점

Protected Power MOSFET



ON Semiconductor 로고
ON Semiconductor
NIF9N05CL 데이터시트, 핀배열, 회로
NIF9N05CL
Protected Power MOSFET
2.6 A, 52 V, N−Channel, Logic Level,
Clamped MOSFET w/ ESD Protection
in a SOT−223 Package
Benefits
High Energy Capability for Inductive Loads
Low Switching Noise Generation
Features
Diode Clamp Between Gate and Source
ESD Protection − HBM 5000 V
Active Over−Voltage Gate to Drain Clamp
Scalable to Lower or Higher RDS(on)
Internal Series Gate Resistance
Pb−Free Packages are Available
Applications
Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
www.DataSheet4U.com
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage Internally Clamped VDSS
52−59
V
Gate−to−Source Voltage − Continuous
VGS ±15 V
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp = 10 ms) (Note 1)
ID
2.6 A
IDM 10
Total Power Dissipation @ TA = 25°C (Note 1) PD
1.69 W
Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C
Single Pulse Drain−to−Source
Avalanche Energy (VDD = 50 V, ID(pk) = 1.17
A, VGS = 10 V, L = 160 mH, RG = 25 W)
EAS
110 mJ
Thermal Resistance,
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RqJA
RqJA
°C/W
74
169
Maximum Lead Temperature for Soldering TL 260 °C
Purposes, 1/8from Case for 10 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to a FR4 board using 1pad size, (Cu area 1.127 in2).
2. When surface mounted to a FR4 board using minimum recommended pad
size, (Cu area 0.412 in2).
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
1
http://onsemi.com
VDSS
(Clamped)
52 V
RDS(ON) TYP
107 mW
ID MAX
2.6 A
Gate
(Pin 1)
Overvoltage
Protection
RG
ESD Protection
Drain
(Pins 2, 4)
MPWR
Source
(Pin 3)
SOT−223
CASE 318E
STYLE 3
MARKING DIAGRAM
GATE
DRAIN
SOURCE
1
2
3
4
DRAIN
(Top View)
A = Assembly Location
Y = Year
W = Work Week
F9N05 = Specific Device Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NIF9N05CL/D


NIF9N05CL 데이터시트, 핀배열, 회로
NIF9N05CL
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = 1.0 mA, TJ = 25°C)
(VGS = 0 V, ID = 1.0 mA, TJ = −40°C to 125°C)
Temperature Coefficient (Negative)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 40 V, VGS = 0 V)
(VDS = 40 V, VGS = 0 V, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = ±8 V, VDS = 0 V)
(VGS = ±14 V, VDS = 0 V)
ON CHARACTERISTICS (Note 3)
IGSS
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 100 mA)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 3.5 V, ID = 0.6 A)
(VGS = 4.0 V, ID = 1.5 A)
(VGS = 10 V, ID = 2.6 A)
Forward Transconductance (Note 3) (VDS = 15 V, ID = 2.6 A)
DYNAMIC CHARACTERISTICS
RDS(on)
gFS
Input Capacitance
Output Capacitance
Transfer Capacitance
VDS = 35 V, VGS = 0 V,
f = 10 kHz
Input Capacitance
Output Capacitance
Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 10 kHz
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperatures.
Ciss
Coss
Crss
Ciss
Coss
Crss
Min
52
50.8
1.3
Typ
55
54
−9.3
±22
1.75
−4.1
190
165
107
3.8
155
60
25
170
70
30
Max
59
59.5
10
25
±10
2.5
380
200
125
250
100
40
Unit
V
V
mV/°C
mA
mA
V
mV/°C
mW
Mhos
pF
pF
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