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PDF EB201D Data sheet ( Hoja de datos )
| Número de pieza | EB201D | |
| Descripción | High Cell Density MOSFETs Low On-Resistance Affords New Design Options | |
| Fabricantes | ON Semiconductor | |
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EB201/D
High Cell Density MOSFETs
Low On–Resistance Affords
New Design Options
Prepared by: Kim Gauen and Wayne Chavez
ON Semiconductor
http://onsemi.com
ENGINEERING BULLETIN
Just a few years ago an affordable 60 V, 10 mΩ power
transistor was a dream. After all, 10 mΩ is the resistance of
about 20 cm of #22 gauge wire. Today a sub–10 mΩ power
MOSFET is not only available, it is housed in a standard
TO–220. Such are the advances that have occurred lately in
“high cell density” power MOSFET technology.
Furthermore, Motorola’s high cell density technology,
HDTMOS®, brings other advantages such as greatly
improved body diode performance. The technological
advances are sufficiently great that they are fundamentally
changing low voltage power transistor technology.
Cutting the MOSFET’s On–Resistance
A cross section of the power MOSFET is shown in
Figure 1. The major contributors to the standard MOSFET’s
SOURCE
GATE
on–resistance are its spreading, channel, JFET,
accumulation region, and substrate resistances. To achieve
ultra–low RDS(on), device designers must decrease the
resistance of all these components. Most of the resistive
elements can be reduced by shrinking cell size and adding
more cells per square centimeter of silicon. However, there
is a limit to maximum packing density. As cell density
becomes very high, on–resistance actually increases due to
a higher JFET resistance. With today’s processes and cell
geometries, the optimum cell density is about five times that
of standard power MOSFETs. Devices built with ON
Semiconductor’s high cell density process (HDTMOS)
employ about 6 M cells/in2, up from the 1.2 M cells/in2 used
in standard power MOSFETs. Figure 2 illustrates the
marked difference in cell density.
SOURCE
R (PACKAGE)
P+
P–
R (ACCUM) R (JFET)
R (CH)
R(N+)
R (METAL)
R (CONTACT)
P+
Nepi
R (SPREAD)
R (BULK)
N + SUBSTRATE
R (SUBSTRATE)
DRAIN
Figure 1. HDTMOS Cross Section
© Semiconductor Components Industries, LLC, 2002
February, 2002 – Rev. 1
1
Publication Order Number:
EB201/D
1 page  
EB201/D
ringing in the parasitic components. Therefore, when
comparing diodes, the ratio of tb/ta serves as a good indicator
of recovery abruptness and thus gives a comparative
estimate of probable noise. So, although the diode recovery
time is only a fraction of the total commutation time, the
noise generated by the diode’s abruptness limits
commutation speeds and determines system switching
losses.
Compared to the diodes of standard cell density
MOSFETs, ON Semiconductor’s high cell density
MOSFET diodes are faster (shorter trr), have less stored
charge, and have a softer reverse recovery (Figure 5).
Figure 6 shows that some high cell density devices are just
as noisy as their predecessors. The softness advantage of
HDTMOS diodes means they can be forced through reverse
recovery at a higher di/dt than that of a standard cell
MOSFET diode without increasing the current ringing or
generating more noise. Generalizing about how much faster
the new diodes can be commutated is difficult since the tb
time is in part a function of circuit layout. However, a
maximum reduction of about 50% seems feasible.
One precaution required when using the body diode of a
high cell density device is that its forward voltage, vf, is
approximately 1 V at elevated current, which is typical of a
p–n junction. Compared to the MOSFET’s Vds(on), vf is
likely to be high. So if the diode’s duty cycle is high, the
on–state losses of the diode must be considered. The diode’s
high forward voltage can be decreased by turning on the
MOSFET when its diode is to conduct. With the gate on,
current flows through the channel (source–to–drain), and
the voltage drop is equal to that of the MOSFET in its
conventional direction.
Switching Speed and Ruggedness
Except for on–resistance and body diode performance,
high cell density devices are very similar to existing
MOSFET technology. For example, the output
characteristics and gate charge curves of high cell density
devices have the same general characteristics as those of
standard devices. For a given die size, HDTMOS devices
require more gate charge than their standard counterparts.
However, for a given on–resistance, HDTMOS devices
have lower gate charge and they switch faster. Standard and
high cell density gate charge waveforms, those of the
MTP50N05E (28 mΩ, 163 mils by 200 mils) and the
MTP75N05HD (9.5 mΩ, 170 mils by 220 mils), are shown
in Figure 7.
Figures 8 and 9 show the switching behavior of the
MTP50N05E and the MTP75N05HD. The HDTMOS
device is slower due to its higher per unit area input
capacitance and larger die area. Had the comparison been
based on the same on–resistance, it would have favored the
HDTMOS device.
di/dt = 100 A/microsecond, lfm = 25 A
IDIODE
MTP75N05HD
0
RFG70N06
20 ns/DIV
Figure 6. Diode Reverse Recovery Compared to
Competition
VGS
MTP50N05E
MTP75N05HD
0
Gate Charge (10 nC/DIV)
Figure 7. Gate Charge Comparison Between
Standard TMOS and HDTMOS
Today’s reliability requirements mandate that all new
high current MOSFETs be rugged with respect to
overvoltage transients that might appear across the
drain–source of the MOSFET. They must be able to handle
avalanche currents of at least their continuous current rating.
HDTMOS devices are no exception to this rule. The
ruggedness of both standard and HDTMOS are limited by
maximum junction temperature, so for a given die area, they
have roughly the same unclamped inductive switching
capability.
http://onsemi.com
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