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Anachip |
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N-Channel Enhancement Mode Power MOSFET
AF4928N
Features
- Low On-resistance
- Simple Drive Requirement
- Dual N MOSFET Package
- Pb Free Plating Product
General Description
The advanced power MOSFET provides the designer
with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
Product Summary
BVDSS (V)
30
RDS(ON) (mΩ)
26
ID (A)
6.8
Pin Assignments
S1 1
G1 2
S2 3
G2 4
SO-8
8 D1
7 D1
6 D2
5 D2
Pin Descriptions
Pin Name
S1/2
G1/2
D1/2
Description
Channel 1/2 Source
Channel 1/2 Gate
Channel 1/2 Drain
Ordering information
A X 4928N X X
Feature
F :MOSFET
PN
Package
S: SO-8
Packing
Blank : Tube or Bulk
A : Tape & Reel
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Oct 13, 2005
1/5
N-Channel Enhancement Mode Power MOSFET
AF4928N
Absolute Maximum Ratings
Symbol
VDS
VGS
Drain-Source Voltage
Gate-Source Voltage
Parameter
ID Continuous Drain Current (Note 1)
IDM
PD
TSTG
TJ
Pulsed Drain Current (Note 2)
Total Power Dissipation
Linear Derating Factor
Storage Temperature Range
Operating Junction Temperature Range
TA=25ºC
TA=70ºC
TA=25ºC
Thermal Data
Symbol
Parameter
Rthj-amb Thermal Resistance Junction-ambient (Note 1)
Max.
Rating
30
±20
6.8
5.5
40
2
0.016
-55 to 150
-55 to 150
Maximum
62.5
Units
V
V
A
A
W
W/ºC
ºC
ºC
Units
ºC/W
Electrical Characteristics at TJ=25ºC unless otherwise specified
Symbol
Parameter
Test Conditions
Min. Typ.
BVDSS
∆BVDSS / ∆TJ
RDS(ON)
VGS(th)
gfs
IDSS
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
RG
Drain-Source Breakdown Voltage VGS=0V, ID=250uA
Breakdown Voltage Temperature Reference to 25oC,
Coefficient
Static Drain-Source
On-Resistance (Note 3)
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current
(TJ=25oC)
Drain-Source Leakage Current
(TJ=70oC)
Gate-Source Leakage
Total Gate Charge (Note 3)
Gate-Source Charge
Gate-Drain (“Miller”) Charge
ID=1mA
VGS=10V, ID=6A
VGS=4.5V, ID=4A
VDS=VGS, ID=250uA
VDS=10V, ID=6A
VDS=30V, VGS=0V
VDS=24V, VGS=0V
VGS=±20V
ID=6.8A,
VDS=24V,
VGS=4.5V
Turn-On Delay Time (Note 3)
Rise Time
Turn-Off Delay Time
Fall-Time
VDS=15V,
ID=1A,
RG=3.3Ω, VGS=10V
RD=15Ω
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V,
VDS=25V,
f=1.0MHz
Gate Resistance
f=1.0MHz
30 -
- 0.03
--
--
1-
- 15
--
--
--
-9
-2
-6
- 10
-9
- 18
-6
- 580
- 150
- 108
- 0.9
Max.
-
-
26
40
3
-
1
25
±100
15
-
-
-
-
-
-
930
-
-
-
Units
V
V/oC
mΩ
V
S
uA
nA
nC
ns
pF
Ω
Source-Drain Diode
Symbol
Parameter
Test Conditions
Min. Typ.
VSD Forward On Voltage (Note 3)
IS=1.7A, VGS=0V
-
trr Reverse Recovery Time (Note 3) IS=6.8A, VGS=0V,
-
Qrr Reverse Recovery Charge
dl/dt=100A/µs
-
Note 1: Surface mounted on 1 in2 copper pad of FR4 board; 135oC/W when mounted on Min. copper pad.
-
15
9
Note 2: Pulse width limited by Max. junction temperature.
Note 3: Pulse width ≤ 300us, duty cycle ≤ 2%.
Max.
1.3
-
-
Unit
V
ns
nC
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Oct 13, 2005
2/5
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