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PDF RF1K49092 Data sheet ( Hoja de datos )
| Número de pieza | RF1K49092 | |
| Descripción | 3.5A/2.5A/ 12V/ 0.050/0.130 Ohm/ Logic Level/ Complementary LittleFET Power MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Data Sheet
January 2002
RF1K49092
3.5A/2.5A, 12V, 0.050/0.130 Ohm, Logic
Level, Complementary LittleFET™ Power
MOSFET
This complementary power MOSFET is manufactured using
an advanced MegaFET process. This process, which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. It is designed for use in applications such as
switching regulators, switching converters, motor drivers,
relay drivers, and low voltage bus switches. This product
achieves full rated conduction at a gate bias in the 3V to 5V
range, thereby facilitating true on-off power control directly
from logic level (5V) integrated circuits.
Formerly developmental type TA49092.
Ordering Information
PART NUMBER
PACKAGE
RF1K49092
MS-012AA
BRAND
RF1K4909 2
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4909296.
Features
• 3.5A, 12V (N-Channel)
2.5A, 12V (P-Channel)
• rDS(ON) = 0.050Ω (N-Channel)
rDS(ON) = 0.130Ω (P-Channel)
• Temperature Compensating PSPICE® Model
• On-Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1 (8)
D1 (7)
S1 (1)
G1 (2)
D2 (6)
D2 (5)
S2 (3)
G2 (4)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
©2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
1 page  
RF1K49092
Typical Performance Curves (N-Channel) (Continued)
25
25oC
-55oC
150oC
VDD = 6V
20
15
10
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0.0 1.5 3.0 4.5 6.0 7.5
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
250
ID = 7.0A
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 10V
150
ID = 3.5A
ID = 1.75A
100
ID = 0.5A
50
0
2.5 3.0 3.5 4.0 4.5 5.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
140
VDD = 6V, ID = 3.5A, RL = 1.71Ω
120
100
80
tr
tD(OFF)
60 tf
40
20
t D(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 3.5A
1.5
1.0
0.5
0.0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0 2.0
VGS = VDS, ID = 250µA
ID = 250µA
1.5 1.5
1.0
0.5
0.0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
1.0
0.5
0.0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RF1K49092 Rev. B
5 Page 
RF1K49092
Soldering Precautions
1. The soldering process creates a considerable thermal
stress on any semiconductor component. The melting
temperature of solder is higher than the maximum rated
temperature of the device. The amount of time the device
is heated to a high temperature should be minimized to
assure device reliability. Therefore, the following precau-
tions should always be observed in order to minimize the
thermal stress to which the devices are subjected.
2. Always preheat the device.
3. The delta temperature between the preheat and soldering
should always be less than 100oC. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
4. The maximum temperature gradient should be less than 5oC
per second when changing from preheating to soldering.
5. The peak temperature in the soldering process should be
at least 30oC higher than the melting point of the solder
chosen.
6. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
7. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
8. During cooling, mechanical stress or shock should be
avoided.
©2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet RF1K49092.PDF ] | |
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