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PDF RF1K49090 Data sheet ( Hoja de datos )

Número de pieza RF1K49090
Descripción 3.5A/ 12V/ 0.050 Ohm/ Logic Level/ Dual N-Channel LittleFET Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RF1K49090
August 1999 File Number 3985.6
3.5A, 12V, 0.050 Ohm, Logic Level, Dual
N-Channel LittleFET™ Power MOSFET
This Dual N-Channel power MOSFET is manufactured using
an advanced MegaFET process. This process, which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. It is designed for use in applications such as
switching regulators, switching converters, motor drivers,
relay drivers, and low voltage bus switches. This product
achieves full rated conduction at a gate bias in the 3V - 5V
range, thereby facilitating true on-off power control directly
from logic level (5V) integrated circuits.
Formerly developmental type TA49090.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49090
MS-012AA
RF1K4909 0
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4909096.
Features
• 3.5A, 12V
• rDS(ON) = 0.050
• Temperature Compensating PSPICE® Model
• On-Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1(8)
D1(7)
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
8-101
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

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RF1K49090 pdf
RF1K49090
Typical Performance Curves (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
2.0
ID = 250µA
1.5
1.0 1.0
0.5 0.5
0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1200
900 VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
600
300
CISS
COSS
CRSS
0
0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
0.0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
12
VDD = BVDSS
9
VDD = BVDSS
5.00
3.75
6 2.50
0.75 BVDSS
0.50 BVDSS
3
0.25 BVDSS
1.25
RL = 3.43
IG(REF) = 0.6mA
VGS = 5V
0 0.00
20 I-I-G-G-----((--AR-----CE----F-T---)-)
t, TIME (µs)
80 -II-G-G-----((--AR-----CE----FT----)-)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
8-105

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