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PDF FQP55N10 Data sheet ( Hoja de datos )

Número de pieza FQP55N10
Descripción 100V N-Channel MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FQP55N10
N-Channel QFET® MOSFET
100 V, 55 A, 26 mΩ
Description
This N-Channel enhancement mode power MOSFET is pro-
duced using Fairchild Semiconductor’s proprietary planar stripe
and DMOS technology. This advanced MOSFET technology has
been especially tailored to reduce on-state resistance, and to
provide superior switching performance and high avalanche en-
ergy strength. These devices are suitable for switched mode
power supplies, audio amplifier, DC motor control, and variable
switching power applications.
November 2013
Features
• 55 A, 100 V, RDS(on) = 26 mΩ (Max.) @ VGS = 10 V,
ID = 27.5 A
• Low Gate Charge (Typ. 75 nC)
• Low Crss (Typ. 130 pF)
• 100% Avalanche Tested
• 175°C Maximum Junction Temperature Rating
D
GDS TO-220
Absolute Maximum Ratings TC = 25°C unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering,
1/8" from Case for 5 seconds
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Junction-to-Ambient, Max.
G
S
FQP55N10
100
55
38.9
220
± 25
1100
55
15.5
6.0
155
1.03
-55 to +175
300
FQP55N10
0.97
62.5
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Unit
°C/W
°C/W
©2000 Fairchild Semiconductor Corporation
FQP55N10 Rev. C1
1
www.fairchildsemi.com

1 page




FQP55N10 pdf
Figure 12. Gate Charge Test Circuit & Waveform
Same Type
50KΩ as DUT
12V 200nF
300nF
VGS
10V
VGS
VDS
Qgs
IG = co3nmsAt.
DUT
Qg
Qgd
Charge
V10GVS
Figure 13. Resistive Switching Test Circuit & Waveforms
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
V1G0GVSS
tp
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS = --21-- L IAS2
------B--V--D--S-S-------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
©2000 Fairchild Semiconductor Corporation
FQP55N10 Rev. C1
5
www.fairchildsemi.com

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