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FDS4410 반도체 회로 부품 판매점

Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET



Fairchild Semiconductor 로고
Fairchild Semiconductor
FDS4410 데이터시트, 핀배열, 회로
April 1998
FDS4410
Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET
General Description
This N-Channel Logic Level MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers.
The MOSFET features faster switching and lower gate
charge than other MOSFETs with comparable RDS(ON)
specifications.
The result is a MOSFET that is easy and safer to drive
(even at very high frequencies), and DC/DC power supply
designs with higher overall efficiency.
Features
10 A, 30 V. RDS(ON) = 0.0135 @ VGS = 10 V
RDS(ON) = 0.0200 @ VGS = 4.5 V.
Optimized for use in switching DC/DC converters
with PWM controllers.
Very fast switching .
Low gate charge (typical 22 nC).
SOT-23
SuperSOTTM-6
SuperSOTTM-8
D
D
D
D
FD44S10
SO-8
pin 1
S
G
S
S
SO-8
SOT-223
5
6
7
8
Absolute Maximum Ratings
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
TA = 25oC unless other wise noted
(Note 1a)
PD Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDS4410
30
±20
10
50
2.5
1.2
1
-55 to 150
50
25
SOIC-16
4
3
2
1
Units
V
V
A
W
°C
°C/W
°C/W
FDS4410 Rev.B1


FDS4410 데이터시트, 핀배열, 회로
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSSF Gate - Body Leakage, Forward
IGSSR Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note 2)
VGS = 0 V, I D = 250 µA
ID = 250 µA, Referenced to 25 oC
30
21
V
mV /oC
VDS = 24 V, VGS = 0 V
1 µA
TJ = 55°C
10 µA
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
100 nA
-100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25 oC
VGS = 10 V, I D = 10 A
VGS = 4.5 V, I D = 9 A
VGS = 10 V, VDS = 5 V
VDS = 10 V, I D= 10 A
TJ =125°C
12
-4.5
3V
mV /oC
0.011 0.0135
0.018 0.023
0.017 0.02
50 A
27 S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
tD(on) Turn - On Delay Time
VDS= 15 V, I D= 1 A
tr Turn - On Rise Time
VGS = 10 V , RGEN = 6 Ω
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
VDS = 15 V, I D = 10 A,
Qgs Gate-Source Charge
VGS = 10 V
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
1340
340
125
pF
pF
pF
12 22 ns
13 24 ns
38 60 ns
10 18 ns
22 31 nC
5 nC
4 nC
IS Maximum Continuous Drain-Source Diode Forward Current
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 2.1 A (Note 2)
2.1
0.73 1.2
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.
a. 50OC/W on a 1 in2 pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
b. 105OC/W on a 0.04 in2
pad of 2oz copper.
c. 125OC/W on a 0.006 in2 pad
of 2oz copper.
FDS4410 Rev.B1




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FDS4410 mosfet

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