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Fairchild Semiconductor |
April 2002
FDG901D
Slew Rate Control Driver IC for P-Channel MOSFETs
General Description
The FDG901D is specifically designed to control the
turn on of a P-Channel MOSFET in order to limit the
inrush current in battery switching applications with high
capacitance loads. During turn-on the FDG901D drives
the MOSFET’s gate low with a regulated current
source, thereby controlling the MOSFET’s turn on. For
turn-off, the IC pulls the MOSFET gate up quickly, for
efficient turn off.
Applications
• Power management
• Battery Load switch
Features
• Three Programmable slew rates
• Reduces inrush current
• Minimizes EMI
• Normal turn-off speed
• Low-Power CMOS operates over wide voltage range
• Compact industry standard SC70-5 surface mount
package
pin 1
GATE 1
SLEW 2
VDD 3
5 GND
4 LOGIC IN
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
Parameter
VDD
VIN
PD
TJ, TSTG
Supply Voltage
DC Input Voltage (Logic Inputs)
Power Dissipation for Single Operation @ 85°C
Operating and Storage Junction Temperature Range
Recommended Operating Range
VDD Supply Voltage
TJ Operating Temperature
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
91
FDG901D
7’’
Ratings
-0.5 to 10
-0.7 to 6
150
-65 to +150
2.7 to 6.0
-40 to +125
425
Tape width
8mm
Units
V
V
mW
°C
V
°C
°C/W
Quantity
3000 units
2002 Fairchild Semiconductor Corporation
FDG901D rev. E (W)
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Logic Levels
VIH Logic HIGH Input Voltage
VIL Logic LOW Input Voltage
OFF Characteristics
BVIN
Logic Input Breakdown Voltage
BVSLEW
Slew Input Breakdown Voltage
BVDG
Supply Input Breakdown Voltage
IRIN
IRSLEW
LOGIC Input Leakage Current
SLEW Input Leakage Current
IRDG Supply Input Leakage Current
ON Characteristics
IG Gate Current
Switching Characteristics
tdon Output Turn-On Delay Time
Slew Pin = OPEN
tdon Output Turn-On Delay Time
Slew Pin = GROUND
tdon Output Turn-On Delay Time
Slew Pin = VDD
trise Output Rise Time
Slew Pin = OPEN
trise Output Rise Time
Slew Pin = GROUND
trise Output Rise Time
Slew Pin = VDD
dv/dt Output Slew Rate
Slew Pin = OPEN
dv/dt Output Slew Rate
Slew Pin = GROUND
dv/dt Output Slew Rate
Slew Pin = VDD
VDD = 2.70V to 6.0 V
VDD = 2.70V to 6.0 V
75%
of VDD
25%
of VDD
V
V
IIN = 10µA, VSLEW = 0 V
ISLEW = 10µA, VIN = 0 V
IDG = 10µA, VIN = 0 V, VSLEW = 0 V
VIN = 8 V, VSLEW = 0 V
VSLEW = 8 V, VIN = 0 V
VDG = 8 V, VIN = 0 V, VSLEW = 0 V
9
9
9
V
V
V
100 nA
100 nA
100 nA
VIN = 6V
VGATE = 2V
SLEW = OPEN
SLEW = GND
SLEW = VDD
90 120
1 10
10 50
µA
µA
nA
VSupply = 5.5 V, VDD = 5.5 V,
Logic IN = 5.5 V,
CLOAD = 510 pF, Test Circuit
VSupply = 5.5 V, VDD = 5.5 V,
Logic IN = 5.5 V,
CLOAD = 510 pF, Test Circuit
VSupply = 5.5 V, VDD = 5.5 V,
Logic IN = 5.5 V,
CLOAD = 510 pF, Test Circuit
8.3 µs
0.6 ms
2.2 ms
28 µs
1.8 ms
11 ms
162 V/ms
2.6 V/ms
0.3 V/ms
Notes: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface
of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
VDD
VSUPPLY
SLEW
2
LOGIC IN
4
3
CLoad
1
5
Test Circuit
LOGIC IN
10%
90%
OUTPUT
(Inverted)
10%
tdon
trise
Switching Waveforms
FDG901D rev. D (W)
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