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FDC6318 반도체 회로 부품 판매점

Dual P-Channel 1.8V PowerTrench Specified MOSFET



Fairchild Semiconductor 로고
Fairchild Semiconductor
FDC6318 데이터시트, 핀배열, 회로
December 2001
FDC6318P
Dual P-Channel 1.8V PowerTrenchSpecified MOSFET
General Description
These P-Channel 1.8V specified MOSFETs are
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize on-state resistance and yet maintain low
gate charge for superior switching performance.
Applications
• Power management
• Load switch
Features
• –2.5 A, –12 V. RDS(ON) = 90 mΩ @ VGS = –4.5 V
RDS(ON) = 125 mΩ @ VGS = –2.5 V
RDS(ON) = 200 mΩ @ VGS = –1.8 V
• High performance trench technology for extremely
low RDS(ON)
• SuperSOTTM-6 package: small footprint (72%
smaller than standard SO-8); low profile (1mm thick)
D2
S1
D1
SuperSOT TM-6
G2
S2
G1
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.318
FDC6318P
13’’
4
5
6
Ratings
–12
±8
–2.5
–7
0.96
0.9
0.7
–55 to +150
130
60
Tape width
12mm
3
2
1
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
3000 units
2001 Fairchild Semiconductor Corporation
FDC6318P Rev D (W)

FDC6318 데이터시트, 핀배열, 회로
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
Drain–Source Breakdown Voltage
∆BVDSS
∆TJ
IDSS
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSSF
Gate–Body Leakage, Forward
IGSSR
Gate–Body Leakage, Reverse
VGS = 0 V,
ID = –250 µA
ID = –250 µA, Referenced to 25°C
VDS = –10 V,
VGS = 8 V,
VGS = –8 V,
VGS = 0 V
VDS = 0 V
VDS = 0 V
On Characteristics (Note 2)
VGS(th)
Gate Threshold Voltage
∆VGS(th)
∆TJ
RDS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID(on)
On–State Drain Current
gFS Forward Transconductance
VDS = VGS,
ID = –250 µA
ID = –250 µA, Referenced to 25°C
VGS = –4.5 V, ID = –2.5 A
VGS = –2.5 V, ID = –2 A
VGS = –1.8 V, ID = –1.6 A
VGS= –4.5 V, ID = –2.5A, TJ=125°C
VGS = –4.5 V, VDS = –5 V
VDS = –5 V, ID = –2.5 A
Dynamic Characteristics
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
VDS = –6 V,
f = 1.0 MHz
V GS = 0 V,
Switching Characteristics
td(on) Turn–On Delay Time
tr Turn–On Rise Time
td(off)
Turn–Off Delay Time
tf Turn–Off Fall Time
Qg Total Gate Charge
Qgs Gate–Source Charge
Qgd Gate–Drain Charge
(Note 2)
VDD = –6 V, ID = –1 A,
VGS = –4.5 V, RGEN = 6 Ω
VDS = –6 V, ID = –2.5 A,
VGS = –4.5 V
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current
VSD
Drain–Source Diode Forward
Voltage
VGS = 0 V,
IS = –0.8 A (Note 2)
–12
–0.4
–6
–2.9
–0.7
2.3
69
93
135
85
8
455
194
134
9
14
21
17
5.4
1.1
1.3
–0.7
V
mV/°C
–1
100
–100
µA
nA
nA
–1.5 V
mV/°C
90 mΩ
125
200
120
A
S
pF
pF
pF
18 ns
25 ns
34 ns
31 ns
8 nC
nC
nC
–0.8
–1.2
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 130 °C/W when
mounted on a 0.125
in2 pad of 2 oz.
copper.
b) 140°C/W when mounted
on a .004 in2 pad of 2 oz
copper
c) 180°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDC6318P Rev D (W)



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FDC6318 mosfet

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