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HUFA75545S3S 반도체 회로 부품 판매점

75A/ 80V/ 0.010 Ohm/ N-Channel/ UltraFET Power MOSFET



Fairchild Semiconductor 로고
Fairchild Semiconductor
HUFA75545S3S 데이터시트, 핀배열, 회로
Data Sheet
HUFA75545P3, HUFA75545S3S
December 2001
75A, 80V, 0.010 Ohm, N-Channel,
UltraFET® Power MOSFET
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
HUFA75545P3
GATE
SOURCE
HUFA75545S3S
Symbol
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.010Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchild.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUFA75545P3
TO-220AB
75545P
HUFA75545S3S
TO-263AB
75545S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75545S3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUFA75545P3, HUFA75545S3S UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous
Continuous
(TC
(TC
=
=
12050oCoC, V, VGGSS==1100VV) )(F(Figiguurere22) )
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ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
80
80
±20
75
73
Figure 4
Figure 6
V
V
V
A
A
Power Dissipation . . .
Derate Above 25oC
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
1. TJ = 25oC to 150oC.
270
1.8
-55 to 175
300
260
W
W/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.mtp.fairchild.com/automotive.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75545P3, HUFA75545S3S Rev. B


HUFA75545S3S 데이터시트, 핀배열, 회로
HUFA75545P3, HUFA75545S3S
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 75V, VGS = 0V
VDS = 70V, VGS = 0V, TC = 150oC
VGS = ±20V
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
VGS(TH)
rDS(ON)
VGS = VDS, ID = 250µA (Figure 10)
ID = 75A, VGS = 10V (Figure 9)
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
RθJC
RθJA
TO-220 and TO-263
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Turn-Off Time
tOFF
GATE CHARGE SPECIFICATIONS
VDD = 40V, ID = 75A
VGS = 10V,
RGS = 2.5
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Qg(TOT)
Qg(10)
Qg(TH)
Qgs
Qgd
VGS = 0V to 20V
VGS = 0V to 10V
VGS = 0V to 2V
VDD = 40V,
ID = 75A,
Ig(REF) = 1.0mA
(Figure 13)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
VSD
trr
QRR
ISD = 75A
ISD = 35A
ISD = 75A, dISD/dt = 100A/µs
ISD = 75A, dISD/dt = 100A/µs
©2001 Fairchild Semiconductor Corporation
MIN TYP MAX UNITS
80 - - V
- - 1 µA
- - 250 µA
- - ±100 nA
2-4
- 0.0082 0.010
V
- - 0.55 oC/W
- - 62 oC/W
- - 210 ns
- 14 - ns
- 125 -
ns
- 40 - ns
- 90 - ns
- - 195 ns
-
195 235
nC
-
105 125
nC
- 6.8 8.2 nC
- 15 - nC
- 43 - nC
- 3750 -
- 1100 -
- 350 -
pF
pF
pF
MIN TYP MAX UNITS
- - 1.25 V
- - 1.00 V
- - 100 ns
- - 300 nC
HUFA75545P3, HUFA75545S3S Rev. B




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HUFA75545S3S mosfet

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75A/ 80V/ 0.010 Ohm/ N-Channel/ UltraFET Power MOSFET - Fairchild Semiconductor