|
|
PDF HUF75542P3 Data sheet ( Hoja de datos )
| Número de pieza | HUF75542P3 | |
| Descripción | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HUF75542P3 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
TM
Data Sheet
HUF75542P3, HUF75542S3S
June 2000 File Number 4845.2
75A, 80V, 0.014 Ohm, N-Channel,
UltraFET Power MOSFETs
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
HUF75542P3
Symbol
GATE
SOURCE
DRAIN
(FLANGE)
HUF75542S3S
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.014Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75542P3
TO-220AB
75542P
HUF75542S3S
TO-263AB
75542S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75542S3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUF75542P3, HUF75542S3S UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
80
80
±20
75
58
Figure 4
Figures 6, 14, 15
V
V
V
A
A
Power Dissipation . . .
Derate Above 25oC
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
PD
...
230
1.54
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
SABER© is a Copyright of Analogy Inc.
1 page  
HUF75542P3, HUF75542S3S
Typical Performance Curves (Continued)
1.2
ID = 250µA
1.1
10000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
1.0 1000 COSS ≅ CDS + CGD
0.9
0.8
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
CRSS = CGD
100
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
80
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 40V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 75A
ID = 50A
ID = 25A
0
0 20 40 60 80 100
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
5
5 Page 
HUF75542P3, HUF75542S3S
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
ØP E
A
Q
H1
D
E1
L1
L
60o
D1
b1
b
12
e
e1
3
45o
c
J1
A1
TERM. 4
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.170
0.180
4.32
4.57
-
A1
0.048
0.052
1.22
1.32
-
b
0.030
0.034
0.77
0.86
3, 4
b1
0.045
0.055
1.15
1.39
2, 3
c
0.014
0.019
0.36
0.48 2, 3, 4
D
0.590
0.610 14.99
15.49
-
D1 - 0.160 - 4.06
E
0.395
0.410 10.04
10.41
-
-
E1
- 0.030 - 0.76
-
e 0.100 TYP
2.54 TYP
5
e1 0.200 BSC
5.08 BSC
H1
0.235
0.255
5.97
6.47
J1
0.100
0.110
2.54
2.79
L
0.530
0.550 13.47
13.97
5
-
6
-
L1
0.130
0.150
3.31
3.81
ØP
0.149
0.153
3.79
3.88
2
-
Q
0.102
0.112
2.60
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HUF75542P3.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HUF75542P3 | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs |  Fairchild Semiconductor |
| HUF75542P3 | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |