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Número de pieza | HUF75309T3ST | |
Descripción | 3A/ 55V/ 0.070 Ohm/ N-Channel UltraFET Power MOSFET | |
Fabricantes | Intersil Corporation | |
Logotipo | ||
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No Preview Available ! Data Sheet
HUF75309T3ST
June 1999
File Number 4377.3
3A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET™ process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75309.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75309T3ST SOT-223
5309
NOTE: HUF75309T3ST is available only in tape and reel.
Features
• 3A, 55V
• Ultra Low On-Resistance, rDS(ON) = 0.070Ω
• Diode Exhibits Both High Speed and Soft Recovery
• Temperature Compensating PSPICE™ Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
DRAIN
(FLANGE)
SOT-223
SOURCE
DRAIN
GATE
23 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET is a trademark of Intersil Corporation. PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page HUF75309T3ST
Typical Performance Curves (Continued)
600
VGS = 0V, f = 1MHz
500
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
400
CISS
300
200
100
0
0
COSS
CRSS
10 20 30 40 50
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
10
WAVEFORMS IN
DESCENDING ORDER:
8
ID = 3A
ID = 1A
VDD = 30V
6
4
2
0
0 2 4 6 8 10 12
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
VDS
RL
VGS
Ig(REF)
DUT
+
VDD
-
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDD
VDS
Qg(TOT)
VGS
VGS = 2V
0
Ig(REF)
0
Qg(10)
Qg(TH)
VGS = 10V
VGS = 20V
FIGURE 17. GATE CHARGE WAVEFORM
27
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet HUF75309T3ST.PDF ] |
Número de pieza | Descripción | Fabricantes |
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