파트넘버.co.kr AF2301PW 데이터시트 PDF


AF2301PW 반도체 회로 부품 판매점

20V P-Channel Enhancement Mode MOSFET



ETC 로고
ETC
AF2301PW 데이터시트, 핀배열, 회로
20V P-Channel Enhancement Mode MOSFET
AF2301P
Features
Product Summary
- Advanced trench process technology
- High density cell design for ultra low on-resistance
- Excellent thermal and electrical capabilities
- Compact and low profile SOT-23 package
VDS = - 20V
RDS (on), VGS@-4.5V, IDS@-2.8A =130m.
RDS (on), VGS@-2.5V, IDS@-2.0A =190m.
Pin Assignments
3
12
(Top View)
1. G
2. S
3. D
Pin Descriptions
Pin Pin
No. Name
1G
2S
3D
Description
Gate
Source
Drain
Ordering information
A X 2301P X X X
Feature
PN Package
Lead Free
Packing
F :MOSFET
W: SOT23 Blank : Normal
Blank : Tube or Bulk
L : Lead Free Package A : Tape & Reel
Block Diagram
DS
G
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.1 Jul 20, 2004
1/4


AF2301PW 데이터시트, 핀배열, 회로
20V P-Channel Enhancement Mode MOSFET
AF2301P
Absolute Maximum Ratings (TA=25ºC unless otherwise noted)
Symbol
VDS
VGS
ID
IDM
PD
TJ
TJ, TSTG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation
Operating Junction Temperature
TA=25ºC
TA=70ºC
Operating Junction and Storage Temperature Range
Rating
-20
±8
-2.3
-10
1.25
0.8
+150
-55 to +150
Thermal Performance
Units
V
V
A
A
W
ºC
ºC
Symbol
Parameter
TL Lead Temperature (1/8” from case)
RθJA Junction to Ambient Thermal Resistance (PCB mounted)
Note: Surface mounted on FR4 board t < 5 sec.
Limit
5
100
Electrical Characteristics Rate ID=-2.3A, (TA=25oC unless otherwise noted)
Symbol
Parameter
Static
BVDSS
Drain-Source Breakdown Voltage
RDS(ON) Drain-Source On-State Resistance
VGS(TH)
IDSS
IGSS
ID(ON)
gfs
Dynamic
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage
On-State Drain Current
Forward Tranconductance
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall-Time
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
Source-Drain Diode
IS Max. Diode Forward Current
VSD Diode Forward Voltage
Note: Pulse test: pulse width < 300uS, duty cycle < 2%
Test Conditions
VGS=0V, ID=-250uA
VGS=-4.5V, ID=-2.8A
VGS=-2.5V, ID=-2.0A
VDS= VGS, ID=-250uA
VDS=-16V, VGS=0V
VGS=±8V, VDS=0V
VDS=-5V, VGS=-10V
VDS=-5V, ID=-2.8A
VDS=-6V, ID=-2.8A,
VGS=-4.5V
VDD=-6V, RL=6,
ID=-1A, VGEN=-4.5V,
RG=6
VDS=-6V, VGS=0V,
f=1.0MHz
IS=-1.6A, VGS=0V
Limits
Min. Typ. Max.
-20 -
-
- 95 130
- 122 190
-0.45 -
-
- - -1.0
- - ±100
-6 -
-
- 6.5 -
- 5.4 10
- 0.8 -
- 1.1 -
- 5 25
- 19 60
- 95 110
- 65 80
- 447 -
- 127 -
- 80 -
- - -1.6
- -0.8 -1.2
Units
S
ºC/W
Unit
V
m
V
uA
nA
A
S
nC
nS
pF
A
V
Anachip Corp.
www.anachip.com.tw
Rev. 1.1 Jul 20, 2004
2/4




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