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Fairchild Semiconductor |
FDG8842CZ
Complementary PowerTrench® MOSFET
April 2007
tm
Q1:30V,0.75A,0.4Ω; Q2:–25V,–0.41A,1.1Ω
Features
Q1: N-Channel
Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A
Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A
Q2: P-Channel
Max rDS(on) = 1.1Ω at VGS = –4.5V, ID = –0.41A
Max rDS(on) = 1.5Ω at VGS = –2.7V, ID = –0.25A
Very low level gate drive requirements allowing direct
operation in 3V circuits(VGS(th) <1.5V)
Very small package outline SC70-6
General Description
These N & P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage applica-
tions as a replacement for bipolar digital transistors and small
signal MOSFETs. Since bias resistors are not required, this dual
digital FET can replace several different digital transistors, with
different bias resistor values.
RoHS Compliant
S2
G2
D1
SC70-6
Pin 1
D2
G1
S1
S1 Q1
G1
D2 Q2
D1
G2
S2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJA
Thermal Resistance, Junction to Ambient Single operation
Thermal Resistance, Junction to Ambient Single operation
Package Marking and Ordering Information
Device Marking
.42
Device
FDG8842CZ
Reel Size
7”
(Note 1a)
(Note 1b)
Q1 Q2
30 –25
±12 –8
0.75 –0.41
2.2 –1.2
0.36
0.30
–55 to +150
Units
V
V
A
W
°C
(Note 1a)
(Note 1b)
350
415
°C/W
Tape Width
8mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
FDG8842CZ Rev.B
1
www.fairchildsemi.com
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
Drain to Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
IDSS Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
ID = –250μA, VGS = 0V
ID = 250μA, referenced to 25°C
ID = –250μA, referenced to 25°C
VDS = 24V, VGS = 0V
VDS = –20V, VGS = 0V
VGS = ±12V, VDS= 0V
VGS = –8V, VDS= 0V
Q1 30
Q2 –25
Q1 25
Q2 –21
Q1
Q2
Q1
Q2
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
rDS(on)
gFS
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On
Resistance
Forward Transconductance
VGS = VDS, ID = 250μA
VGS = VDS, ID = –250μA
ID = 250μA, referenced to 25°C
ID = –250μA, referenced to 25°C
VGS = 4.5V, ID = 0.75A
VGS = 2.7V, ID = 0.67A
VGS = 4.5V, ID = 0.75A ,TJ = 125°C
VGS = –4.5V, ID = –0.41A
VGS = –2.7V, ID = –0.25A
VGS = –4.5V, ID = –0.41A ,TJ = 125°C
VDS = 5V, ID = 0.75A
VDS = –5V, ID = –0.41A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
0.65
–0.65
1.0
–0.8
–3.0
1.8
0.25
0.29
0.36
0.87
1.20
1.22
3
8
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Q1
VDS = 10V, VGS = 0V, f= 1MHZ
Q2
VDS = –10V, VGS = 0V, f= 1MHZ
Q1
Q2
Q1
Q2
Q1
Q2
90
70
20
30
15
15
Switching Characteristics (note 2)
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qgs Gate to Source Charge
Qgd Gate to Drain “Miller” Charge
Q1
VDD = 5V, ID = 0.5A,
VGS = 4.5V,RGEN = 6Ω
Q2
VDD = –5V, ID = –0.5A,
VGS = –4.5V,RGEN = 6Ω
Q1
VGS =4.5V, VDD = 5V, ID = 0.75A
Q2
VGS = –4.5V, VDD = –5V, ID = –0.41A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
4
6
1
16
9
35
1
40
1.03
1.20
0.29
0.31
0.17
0.22
Max Units
V
1
–1
±10
–100
mV/°C
μA
μA
nA
1.5
–1.5
0.4
0.5
0.6
1.1
1.5
1.9
V
mV/°C
Ω
S
120
100
pF
30
40
pF
25
25
pF
10
12
10
29
18
56
10
64
1.44
1.68
ns
ns
ns
ns
nC
nC
nC
©2007 Fairchild Semiconductor Corporation
FDG8842CZ Rev.B
2
www.fairchildsemi.com
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