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PDF FDS4897AC Data sheet ( Hoja de datos )
| Número de pieza | FDS4897AC | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
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FDS4897AC
October 2008
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 40 V, 6.1 A, 26 mΩ P-Channel: -40 V, -5.2 A, 39 mΩ
Features
General Description
Q1: N-Channel
Max rDS(on) = 26 mΩ at VGS = 10 V, ID = 6.1 A
Max rDS(on) = 31 mΩ at VGS = 4.5 V, ID = 5.6 A
Q2: P-Channel
Max rDS(on) = 39 mΩ at VGS = -10 V, ID = -5.2 A
Max rDS(on) = 65 mΩ at VGS = -4.5 V, ID = -4.1 A
100% UIL Tested
RoHS Compliant
These dual N- and P-Channel MOSFETs are produced using
Fairchild Semiconductor's advanced PowerTrench® process
that has been especially tailored to minimize on-state resistance
and yet maintain superior switching performance.
Applications
Inverter
Power Supplies
D2
D2
D1
D1
Pin 1
G2
S2
G1
S1
SO-8
D2 5
D2 6
D1 7
D1 8
Q2
Q1
4 G2
3 S2
2 G1
1 S1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
EAS
TJ, TSTG
Single Pulse Avalanche Energy
Operating and Storage Junction Temperature Range
Thermal Characteristics
TA = 25 °C (Note 1a)
TA = 25 °C (Note 1b)
(Note 3)
Q1 Q2
40 -40
±20 ±20
6.1 -5.2
24 -24
2.0
1.6
0.9
37 73
-55 to +150
Units
V
V
A
W
mJ
°C
RθJC
RθJC
Thermal Resistance, Junction to Case,
Thermal Resistance, Junction to Ambient,
Package Marking and Ordering Information
(Note 1)
(Note 1a)
40
78
°C/W
Device Marking
FDS4897AC
Device
FDS4897AC
Package
SO-8
Reel Size
13 ”
Tape Width
12 mm
Quantity
2500 units
©2008 Fairchild Semiconductor Corporation
FDS4897AC Rev.C
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 6.1 A
8
VDD = 15 V
6
VDD = 20 V
VDD = 25 V
4
2
0
0 4 8 12 16
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
Crss
f = 1 MHz
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
40
Figure8. CapacitancevsDrain
to Source Voltage
10
9
8
7
6
5
4
3
TJ = 125 oC
TJ = 25 oC
2
1
0.01
0.1 1
tAV, TIME IN AVALANCHE (ms)
10 20
Figure9. UnclampedInductive
Switching Capability
7
6
5
VGS = 10 V
4
VGS = 4.5 V
3
2
1
RθJA = 78 oC/W
0
25 50
75
100 125
TC, AMBIENT TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Ambient Temperature
30
10
100 us
1
0.1
0.01
0.01
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
RθJA = 135 oC/W
TA = 25 oC
0.1 1 10
VDS, DRAIN to SOURCE VOLTAGE (V)
1s
10 s
DC
100 200
Figure 11. Forward Bias Safe
Operating Area
1000
VGS = 10 V
100
10
SINGLE PULSE
RθJA = 135 oC/W
TA = 25 oC
1
0.5
10-4 10-3 10-2 10-1
1
10 100 1000
t, PULSE WIDTH (sec)
Figure 12. Single Pulse Maximum
Power Dissipation
©2008 Fairchild Semiconductor Corporation
FDS4897AC Rev.C
5
www.fairchildsemi.com
5 Page 
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