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PDF SH-1 Data sheet ( Hoja de datos )
| Número de pieza | SH-1 | |
| Descripción | (SH-1 / SH-2) 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH-1 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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Introduction
The SH-1 and SH-2 incorporates a RISC (Reduced Instruction Set Computer) type CPU. A basic
instruction can be executed in one clock cycle, realizing high performance operation. A built-in
multiplier can execute multiplication and addition as quickly as DSP.
The SH-DSP is a 32 bit microcontroller based on Renesas SuperHTM RISC engine that realizes the
same signal processing capability as a general usage DSP (Digital Signal Processor). The SH-DSP
offers an improvement on the DSP functions of multiplication and multiply and accumulate in
SuperH microprocessors by using a DSP style data path function. It maintains upward
compatibility at the object code level with the SH-1 and SH-2 microprocessors and has the many
functions, low power usage, and low price of other SuperH microprocessors.
The SH-DSP achieves high performance in processing operations by using a RISC CPU core and
a DSP unit with DSP functions. This new type of single chip RISC-DSP simultaneously integrates
the peripheral functions needed to build systems into the SH-DSP and provides the lower-power
consumption vital to microprocessor applications.
This Software Manual describes in detail the basic architecture and instructions for the SH-1, SH2,
and SH-DSP and is intended as a reference on instruction operation and architecture. It also covers
the operation of pipelines, which are a feature of the SuperH microprocessor.
For software development environment system, contact your Renesas Technology Corp. sales
office.
Note: SuperHTM is a trademark of Renesas Technology Corp.
Rev. 5.00 Jun 30, 2004 page iii of xiv
REJ09B0171-0500O
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5.1.4 Shift Instructions.................................................................................................. 103
5.1.5 Branch Instructions .............................................................................................. 104
5.1.6 System Control Instructions................................................................................. 105
5.1.7 CPU Instructions That Support DSP Functions ................................................... 108
5.2 DSP Data Transfer Instruction Set .................................................................................... 111
5.2.1 Double Data Transfer Instructions (X Memory Data) ......................................... 112
5.2.2 Double Data Transfer Instructions (Y Memory Data) ......................................... 112
5.2.3 Single Data Transfer Instructions......................................................................... 113
5.3 DSP Operation Instruction Set .......................................................................................... 115
5.3.1 ALU Arithmetic Operation Instructions .............................................................. 118
5.3.2 ALU Logical Operation Instructions ................................................................... 122
5.3.3 Fixed Decimal Point Multiplication Instructions ................................................. 122
5.3.4 Shift Operation Instructions ................................................................................. 123
5.3.5 System Control Instructions................................................................................. 124
5.3.6 NOPX and NOPY Instruction Code .................................................................... 125
Section 6 Instruction Descriptions.................................................................................. 127
6.1 Instruction Descriptions .................................................................................................... 127
6.1.1 Sample Description (Name): Classification......................................................... 127
6.1.2 ADD (ADD Binary): Arithmetic Instruction ....................................................... 131
6.1.3 ADDC (ADD with Carry): Arithmetic Instruction .............................................. 132
6.1.4 ADDV (ADD with V Flag Overflow Check): Arithmetic Instruction................. 133
6.1.5 AND (AND Logical): Logic Operation Instruction ............................................. 135
6.1.6 BF (Branch if False): Branch Instruction............................................................. 137
6.1.7 BF/S (Branch if False with Delay Slot): Branch Instruction................................ 139
6.1.8 BRA (Branch): Branch Instruction ...................................................................... 141
6.1.9 BRAF (Branch Far): Branch Instruction.............................................................. 143
6.1.10 BSR (Branch to Subroutine): Branch Instruction................................................. 145
6.1.11 BSRF (Branch to Subroutine Far): Branch Instruction ........................................ 147
6.1.12 BT (Branch if True): Branch Instruction.............................................................. 149
6.1.13 BT/S (Branch if True with Delay Slot): Branch Instruction ................................ 151
6.1.14 CLRMAC (Clear MAC Register): System Control Instruction ........................... 153
6.1.15 CLRT (Clear T Bit): System Control Instruction................................................. 154
6.1.16 CMP/cond (Compare Conditionally): Arithmetic Instruction.............................. 155
6.1.17 DIV0S (Divide Step 0 as Signed): Arithmetic Instruction................................... 159
6.1.18 DIV0U (Divide Step 0 as Unsigned): Arithmetic Instruction .............................. 160
6.1.19 DIV1 (Divide 1 Step): Arithmetic Instruction ..................................................... 161
6.1.20 DMULS.L (Double-Length Multiply as Signed): Arithmetic Instruction ........... 166
6.1.21 DMULU.L (Double-Length Multiply as Unsigned): Arithmetic Instruction....... 168
6.1.22 DT (Decrement and Test): Arithmetic Instruction ............................................... 170
Rev. 5.00 Jun 30, 2004 page ix of xiv
REJ09B0171-0500O
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet SH-1.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SH-1 | (SH-1 / SH-2) 32-Bit RISC Microcomputer | Renesas Technology |
| SH-2 | (SH-1 / SH-2) 32-Bit RISC Microcomputer | Renesas Technology |
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