6501 판매점 - ONE-CHIP MICROCOMPUTER

6501 반도체 회로 부품 판매점

ONE-CHIP MICROCOMPUTER

Commodore

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~ aarnlconduCl:ar group

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MPS

6500/1

ONE-CHIP

MICROCOMPUTER

8500/1 ONE-CHIP MICROCOMPUTER

INTRODucnoN

The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and

Is totally upward/downward software compatible with all members of the 6500 family.

The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes

of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt

programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-

sensitive lines), five Interrupts and a counter I/O line.

PRODUCT SUPPORT

To allow prototype clrCl~lt development, Mos Tech-

nology offers a PROM compatible 64-pln Emulator de-

vice. This device provides all 650011 Interface lines

plus routing the address bus, data bus, and asso-

ciated control lines off the chip to be connected to

external memory.

Order

Number

ORDERING INFORMATION

Package Frequency Temperature

Type Option

Range

MPS65OOI1

Plastic 1 MHz

MCS6500/1 Ceramic 1 MHz

MPS65OOI1A Plastic 2 MHz

MCS65OOI1A Ceramic 2 MHz

MCS65OOI1E Emulator Device 1MHz

'MCS65OOI1EA Emulator Device 2MHz

O°C to 70°C

Note: The RC frequency option is available only in the

1 MHz 6500/1.

XTU

)(flO

RES

Rgj

vee

vss

VRR

¢a;> PAO-PA7

¢a~ P8(H2B7

¢a ~ pc()'PC7

¢a::> POOPD7

CNTR

FEATURES

• 6502 CPU

-Software upward/downward compatibility

-Decimal or binary arithmetic modes

-13 addressing modes

-True direct and indirect indexing

-Memory addressable 110

• 2048 x 8 mask programmable ROM

• 64 x 8 static RAM

• 32 bi<iirectional TIL compatible 110 lines (4 ports)

• 1 bi<iirectional TIL compatible counter I/O line

• 16-bit programmable counter/latch with four

modes

-Interval Timer -Event Counter

-Pulse Generator -Pulse Width Measurement

• Five Interrupts

-Reset

-Non·maskable

-Two external edge sensitive

-Counter

• 1 of 3 frequency references

-Crystal -Clock -RC (resistor only)

• 4 MHz max crystal or clock external frequency

• 2 MHz or 1 MHz internal clock

• 1 /Ls minimum instruction execution

• N-channel, silicon gate, depletion load technology

• Single + 5V power supply

• 500 mW operating power

• Separate power pin for RAM

• 40 pin DIP

• 64 pin PROM compatible Emulator device

Interface Diagram

2-2

FUNCTIONAL DESCRIPTION

CENTRAL PROCESSING UNIT (CPU)

Clock OIcIllator

The Clock Oscillator provides the basic timing

Signals used by the 6500/1 CPU. The reference fre-

quency Is provided by an external source, and can be

from a crystal, clock or RC network Input. The RC net·

work mode Is a mask option. The external frequency

can vary from 200 kHz to 4 MHz. The Internal Phase 2

(02) frequency Is one-half the external reference fre-

quency. A 4.7K ohm resistor will provide nominal 2

MHz oscillation and 1 MHz Internal operation In the

RC mask option (±35%).

TIming Control

The Timing Control Logic keeps track of the

specific Instructlo:1 cycle being executed. Each data

transfer which takes place between the registers Is

caused by decoding the contents of both the Instruc·

tlon Register and Timing Control Logic.

Program Counter

The 16-blt Program Counter provides the addresses

which step the CPU through sequential Instructions

In a program. The Program Counter Is Incremented

each time an instruction or data Is fetched from

memory.

Instruction Register and Decode

Instructions fetched from memory are gated onto

the Internal Data Bus. These Instructions are iatched

Into the Instruction Register then decoded, along with

timing and Interrupt Signals, to generate controi

Signals for the various registers.

ArIthmetic and Logic Unit (ALU)

All arithmetic and logic operations take place In the

ALU, including incrementing and decrementing Inter·

nal registers (except the Program Counter).

Accumulator

The accumulator Is a general purpose 8-blt register

that stores the results of most arithmetic and logic

operations. In addition, the accumulator usually con·

talns one of the two data words used In these opera·

tlons.

Index Registers

There are two 8-blt Index registers, X and Y. These

registers can be used for general purpose storage, or

as a displacement to modify the base address and

thus obtain a new effective address. Pre· or post·

indexing of Indirect addresses is possible.

Stack Pointer

The Stack Pointer is an 8-blt register. it Is automat·

ically incremented and decremented under control of

the CPU to perform stack manlpuiatlon under d~·

tlon of either the program or interrupts NMI and IRQ.

The stack allows simple Implementation of nested

subroutines and multiple level interrupts.

lNJV/

MPS

6500/1

/B/O/I Z C

,,'~.,'"=1 Carry Set

0= Carry CI••r

ITSZERO (Z)(1)

=1 Zero Result

l:= =o Non-Zero Result

INTERRUPT DISABLE (1) (2)

1 = IRQ Interrupt Disabled

o = IRQ Interrupt Enabled

DECIMAL MODE (D) (1)

=1 Decimal Mode

o = Binary Mode

BREAK COMMAND (B) (1)

=, = Break Command

o Not Break Command

OVERFLOW (0) (1)

1 = Overflow set

Q = Overflow Clear

NOTES:

(1) Not initialized by RES

(2) Set to Logic 1 by REs

NEGATIVE (N) (1)

1 = Negative Value

o = Positive Value

Processor Status Register

The 8-blt Processor Status Register contains seven

status flags. Some of the flags are controlled by the

program, others may be controlled both by the pro-

gram and the CPU. The 6500 Instruction set contains

a number of conditional branch Instructions which

are designed to allow testing of these flags.

Interrupt Logic

Interrue!..!9glc controls the sE!Cluenclng of three In·

terrupts; RES, ~ and !'RO. iRQ Is generated by any

one of three conditions: Counter Overflow, PAO

Positive Edge Detected, and PA1 Negative Edge De-

tected.

MEMORY

2048 x 8 ROM

The 2048 byte Read-Only Memory (ROM) contains

the program instructions and other fixed constants.

These program Instructions and constants are mask

programmed Into the ROM during fabrication of the

6500/1 device. The 650011 ROM is memory mapped

from 800 to FFF.

64 x 8 RAM

The 64 byte Random Access Memory (RAM) Is used

for read/write memory during system operation, and

contains the stack. This RAM is completely static in

operation and requires no clock or dynamic refresh. A

standby power pin, VRR, allows RAM memory to be

maintained on 10% of the operating power In the

event that VCC power Is lost.

In order to take advantage of efficient zero page ad·

dressing capabilities, the RAM is assigned memory

addresses 0 to 03F.

2-3

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6501 microcomputer

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6501 반도체 회로 부품 판매점

ONE-CHIP MICROCOMPUTER

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