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PDF A6281 Data sheet ( Hoja de datos )
| Número de pieza | A6281 | |
| Descripción | 3-Channel Constant Current LED Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de A6281 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
Features and Benefits
▪ 3 × 10-bit PWM brightness settings
▪ 3 × 7-bit dot correction current settings
▪ 5 to 17 V operation
▪ Wide output current range, 10 to 150 mA per channel
▪ Internally generated PWM clock
▪ Serial port operates at up to 5 MHz
▪ Data and clock logic architecture allows single
www.DataSheet4Um.ciocmrocontroller control of large quantities of serially-
connected A6281s at fast data transfer rate
▪ Buffered logic outputs to drive cables
▪ Thermal shutdown and UVLO protection
▪ Power-On Reset
Package: 16-terminal QFN (suffix ES)
3 mm x 3 mm footprint
Description
The A6281 is a 3-channel constant current LED driver that
has a wide range of output currents. The A6281 controls LED
brightness with a Pulse Width Modulation (PWM) scheme
that gives the application the capability of displaying a billion
colors in an RGB cluster. The maximum current is set by an
external resistor.
The LED brightness is controlled by performing PWM control
on the outputs. The brightness data of the PWM signal for
each LED is stored in three 10-bit registers. The peak value
for each LED can be adjusted (dot-corrected) to compensate
for mismatch, aging, and temperature effects. All the internal
latched registers are loaded by a 32-bit shift register. One
address bit controls whether dot correction/clock divider ratio
or brightness data is loaded into the registers. The remaining
bits are used for the data.
TheA6281 is designed to minimize the number of components
needed to drive LEDs with large pixel spacing. A large number
of A6281s can be daisy chained together and controlled by
just four control signals (clock, serial data, latch, and output
enable). Each of these inputs is buffered to drive the next chip
in the chain. Also, VIN can be tied to the LED voltage supply
Continued on the next page…
Power Supply Bus
Clock
Data
Latch
Output Enable
Microprocessor
Control Board
Cat5 UTP
Application Diagram
VLED
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Latch In
Latch Out
OE In
OE Out
VREG A6281 REXT
Pixel Board #1
Cat5 UTP
VLED
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Latch In
Latch Out
OE In
OE Out
VREG A6281 REXT
Pixel Board #2
Cat5 UTP
Pixel Board #N
Figure 1. Functional drawing of daisy chained display application. Additional pixel boards
with A6281 ICs can be applied.
A6281-DS, Rev. 1
1 page  
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
www.DataSheet4U.com
CI
(External Clock)
tSU (D )
SDI
(Serial Data In)
0 12345678
tw(C L K)
tH( D)
D31 D30 D29 D28 D27 D26 D25 D24 D23
SDO
(Serial Data Out)
Don’t Care
LI
(Latch In)
LO
(Latch Out)
Figure 2. Serial Port Timing
15 16
D16 D15
31
D0
tSU (L I )
tP(SD O)
D31
tH (L I )
tP(IO)
Internal Oscillator or
CI (External Clock)
PWM Counter
0
IOUT0
Brightness Data= 0
IOUT1
Brightness Data= 1
tP(OE)
IOUT2
Brightness Data = 1022
OEI
(Output Enable Input)
OEO
(Output Enable Output)
tP(IO)
T1 T2
12
TN
1023 0 1 2
tP(OUT)
tP(OUT)
Outputs Off
Outputs On
tw (OE)
tP(OUT)
Figure 3. PWM Counter and Output Timing
X0
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
www.DataSheet4U.com
3.00 ±0.15
16
1A
2
ES Package, 16 Pin QFN
0.30
0.90 16
3.00 ±0.15
1
0.50
1.70 3.10
17X D
0.08 C
0.25
+0.05
–0.07
0.50
0.40
+0.15
–0.10
2
1
B
16
1.70
SEATING C
PLANE
0.75 ±0.05
1.70
3.10
C PCB Layout Reference View
For reference only
(reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
1.70 B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Copyright ©2006-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet A6281.PDF ] | |
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