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PDF BD81A34EFV-M Data sheet ( Hoja de datos )
| Número de pieza | BD81A34EFV-M | |
| Descripción | 4ch White LED Driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
4ch White LED Driver with Buck-Boost
(32 LED Maximum)
BD81A34MUV-M BD81A34EFV-M
General Description
BD81A34MUV-M/EFV-M is a white LED driver with the capability of
withstanding high input voltage (35V Max). This driver has 4ch
constant-current drivers integrated in 1-chip, where each channel
can draw up to 120mA (Max), which is also suitable for high
illumination LED drive. Furthermore, a buck-boost current mode
DC/DC controller is also integrated to achieve stable operation
during power voltage fluctuation. Light modulation (dimming
function) is possible by PWM input.
Key Specifications
Operating Input Voltage Range
Output LED Current Accuracy
DC/DC Oscillation Frequency
Operating Temperature Range
LED Maximum Output Current
4.5 to 35 V
±3.0%@50mA
200 to 2200kHz
-40 to +125
120mA/ch
Features
Integrated Buck-Boost current mode DC/DC controller
Integrated 4ch current driver for LED drive
PWM light modulation (Dimming)-supported
External switching frequency synchronization
Built-In protection function (UVLO, OVP, OCP, SCP)
LED abnormality detection function (Open/Short)
Integrated VOUT discharge function (Buck-Boost structure
limitation)
AEC-Q100 Qualified
Package(s) W(Typ) x D(Typ) x H(Max)
VQFN28SV5050
HTSSOP-B28
(BD81A34MUV-M)
(BD81A34EFV-M)
W×L×H
W×L×H
5.0 ×5.0 ×1.0
9.7 ×6.4 ×1.0
Application
Audio Display , Navi , CID , Cluster , HUD
Small and Medium type LCD Panels for Automotive use.
Application Circuit Diagram
CIN
Vin
(GND)
(GND)
CREG
(GND)
VCC
EN
VREG
VDISC
SYNC
RT
RRT
(GND)
COMP
RPC
CPC
(GND)
SS
CSS
(GND)
PWM
BD81A34MUV-M
ISET
RISET
(GND)
GND
(GND)
LEDEN1 LEDEN2
Product structure Silicon monolithic integrated circuit
This product has no designed protection against radioactive rays
OVP
FB
CS
FAIL1
BOOT
OUTH
SW
(DGND)
OUTL
DGND
(DGND)
LED1
LED2
LED3
LED4
PGND
(PGND)
FAIL2
COUT
(DGND)
(DGND) (DGND)
(DGND)
Figure 1. Buck-Boost Application Circuit
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 14 001
1/33
TSZ02201-0G3G0C600020-1-2
16.Jan.2014 Rev.002
1 page  
BD81A34MUV-M BD81A34EFV-M
Datasheet
(Unless otherwise specified, VCC=12V, Ta = Tj = -40 ~ 125 )
Parameters
Symbol
Standard Value
MIN TYP MAX
[FB Section]
FB detection voltage
VFB 0.9 1.0 1.1
Unit Condition
V VFB=Sweep up
FB hysteresis width
[UVLO Section]
UVLO detection voltage
VFBHYS
VUVLO
0.33
0.43
0.53
V VFB=Sweep down
3.2 3.5 3.8 V VCC : Sweep down
UVLO hysteresis width
[LED Output Section]
LED current relative deviation
width
VUHYS
∆ILED1
LED current absolute
deviation width
∆ILED2
ISET voltage
PWM dimmer MIN pulse width
VISET
TMin
250 500 750 mV VCC : Sweep up, VREG>3.5V
-3
-
+3
%
ILED=50mA, Ta=25
∆ILED1=(ILED/ILED_AVG-1)×100
-5
-
+5
%
ILED=50mA
∆ILED1=(ILED/ILED_AVG-1)×100
-3
-
+3
%
ILED=50mA, Ta=25
∆ILED2=(ILED/50mA-1)×100
-5
-
+5
%
ILED=50mA
∆ILED2=(ILED/50mA-1)×100
0.9 1.0 1.1 V RISET=100kΩ
20 -
- μs FPWM=150Hz, ILED=100mA
PWM dimmer Max dim
DMax - - 100 % FPWM=150Hz, ILED=50mA
PWM dimmer frequency
[Protection Circuit Section]
FPWM
-
- 20 kHz Duty=2%, ILED=50mA
LED open detection voltage VOPEN 0.2 0.3 0.4 V VLED= Sweep down
LED short detection voltage
VSHORT
4.2
4.5
LED short detection
latch OFF delay time
TSHORT 70 100
PWM Latch OFF delay time
TPWM
70 100
SCP Latch OFF delay time
TSCP
70 100
[Logic Input Voltage] (EN, PWM, SYNC, LEDEN1 & LEDEN2)
Input High voltage
VINH 2.1 -
4.8 V VLED= Sweep up
130 ms RRT=27kΩ
130 ms RRT=27kΩ
130 ms RRT=27kΩ
VREG
V
Input Low voltage
Input flow current
[FAIL Output (Open drain)]
FAIL Low voltage
VINL
IIN
VOL
- - 0.8 V
Apply at 5V
15 50 100 μA (EN,SYNC,PWM,LEDEN1,
LEDEN2)
- 0.1 0.2 V IOL=0.1 A
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
5/33
TSZ02201-0G3G0C600020-1-2
16.Jan.2014 Rev.002
5 Page 
BD81A34MUV-M BD81A34EFV-M
Datasheet
4. Self-Check Function
Table 2. Detection Condition of Each Protection Function and the Operation during Detection
Protection Function
Detection Condition
[Detection ]
[Release/ Cancellation]
Operation During Detection
UVLO
TSD
VCC<3.5V or VREG<2.0V
Tj>175°C
VCC >4.0V and VREG>3.5V
Tj<150°C
All Blocks Shuts down
(Except for VREG)
All Blocks Shuts down
(Except for VREG)
OVP
VOVP>2.0V
VOVP<1.45V
SS Pin Discharged
OCP
VCS VCC-0.6V
SCP
VLED<0.3V
or
VOVP<0.57V
(100ms delay @300kHz)
LED Open Protection
LED Short Protection
VLED<0.3V
& VOVP>1.7V
VLED>4.5V
(100ms delay @300kHz)
Note1. The FAIL1 and FAIL2 output is reset when EN=Low
EN Low or UVLO Detection are unfixed.
VCS>VCC-0.6V
EN or UVLO
EN or UVLO
EN or UVLO
High or UVLO Detection
SS Pin Discharged
Delay Counter starts and then
Latches Off all blocks
(Except for VREG)
Only the detected channel latches
OFF
Only the detected channel latches
OFF (After the counter starts )
Release/ Cancel
FFAAIILL11
FFAAIILL2
EN=Low or UVLO
EN=Low or UVLO
Figure 17. Protection Flag Output Block Diagram
The operating status of the built-in protection circuitry is propagated to FAIL1 and FAIL2 terminals (open-drain outputs).
FAIL1 becomes low when TSD, OVP, OCP, or SCP protection is engaged, whereas FAIL2 becomes low when open or
short LED is detected. If the FAIL terminal will not be used as flag output, please make the FAIL terminal open or connect it
to GND. But if the FAIL terminal will be used as a flag output, it is recommended to pull-up the FAIL1, 2 terminals to VREG
terminal.
(1) Under-Voltage Lock Out (UVLO)
The UVLO shuts down all the circuits other than VREG when VCC<3.5V(Typ) or VREG <2.0V(Typ)
(2) Thermal Shut Down (TSD)
The TSD shuts down all the circuits other than VREG when the Tj reaches 175°C (Typ), and releases when the Tj
becomes below 150°C (Typ).
(3) Over-Current Protection (OCP)
The OCP detects the current through the power-FET by monitoring the voltage of the high-side resistor, and activates
when the CS voltage becomes less than VCC-0.6V (Typ).
When the OCP is activated, the external capacitor of the SS terminal becomes discharged and the switching operation
of the DC/DC turns off.
(4) Over-Voltage Protection (OVP)
The output voltage of DC/DC is detected from the OVP terminal voltage, and the over-voltage protection will activate if
the OVP terminal voltage becomes greater than 2.0V (Typ). When OVP is activated, the external capacitor of the SS
terminal becomes discharged and the switching operation of the DC/DC turns off.
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
11/33
TSZ02201-0G3G0C600020-1-2
16.Jan.2014 Rev.002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BD81A34EFV-M.PDF ] | |
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