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PDF QD12TL02 Data sheet ( Hoja de datos )
| Número de pieza | QD12TL02 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Quanta | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de QD12TL02 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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Preliminary
Quanta Display Inc.
SPECIFICATION
3&6. 2CIG
Doc No. QD12TL0201
Doc. REV.: 01
Issue Date: 8/29/2005
With RoHS
Compliant
Specification for TFT LCD Module
Model No.
QD12TL02 Rev.:01
Approved By
Quanta Display Inc.
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4. Input Connectors
3&6. 2CIG
4-1 Signal Interface Connector
CN1 (1 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: DF19L-20P-1H by Hirose or equivalent
Interface Cable Pin Assignments
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
FUNCTION
VSS Ground
VDD Power Supply, 3.3 V (typical)
VDD Power Supply, 3.3 V (typical)
V EEDID
DDC 3.3V power
NC Reserved for supplier test point
Clk EEDID DDC Clock
DATA EEDID DDC Data
Rin0-
- LVDS differential data input (R0-R5, G0) (odd pixels)
Rin0+
+ LVDS differential data input (R0-R5, G0) (odd pixels)
VSS Ground
Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
VSS Ground
Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
VSS Ground
ClkIN-
- LVDS differential clock input (odd pixels)
ClkIN+
+ LVDS differential clock input (odd pixels)
VSS Ground
NC No connect
[Note 1] Relation between LVDS signals and actual data shows below section (4-2).
[Note 2] The shielding case is connected with signal GND.
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7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
Data
ENAB
Sync
3&6. 2CIG
ዞ
ዟዠ
ዡ
ዝ
ዢ
ዄ Vertical ዅ
Itemዄsymbolዅ
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back
porch (TVC+TVD)
Active display area (TVE)
Front porch (TVF)
Min.
808
8
2
2
4
800
2
Typ.
16.667
816
16
4
8
12
800
4
Max.
900
100
20
80
100
800
80
Unit Remark
ms Negative
line
line
line
line
line
line
line
( Horizontal )
Itemዄsymbolዅ
Min.
Typ.
Max. Unit Remark
Hsync cycle (THA)
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
1340
60
16
20
36
1280
8
20.44
1408
128
32
75
107
1280
21
1600
320
48
180
228
Ǵs
clock
clock
clock
clock
clock
Negative
1280
180
clock
clock
ዄClock ዅ
Item
Min.
Typ.
Max. Unit Remark
Frequency
60 68.9 80 MHz [Note1]
[Note] In case of lower frequency, the deterioration of display quality, flicker etc., may be
occurred.
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet QD12TL02.PDF ] | |
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