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PDF V400H1-P08 Data sheet ( Hoja de datos )
| Número de pieza | V400H1-P08 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CMI MEI | |
| Logotipo |  |
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PRODUCT SPECIFICATION
ϭʳ Tentative Specification
ϭʳ Preliminary Specification
Ϯʳ Approval Specification
MODEL NO.: V400H1
SUFFIX: P08
Customer:
APPROVED BY
Name / Title
Note
SIGNATURE
Please return 1 copy for your confirmation with your
signature and comments.
Approved By
Chao-Chun Chung
Checked By Prepared By
Josh Chi Joanne Chung
Version 2.0
1 DateΚ9 Jun 2010
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
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PRODUCT SPECIFICATION
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V400H1-P08 is a 40” TFT Liquid Crystal Display cell with driver ICs and 2ch-LVDS interface. This product
supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit colors). The backlight unit is not
built-in.
1.2 FEATURES
CHARACTERISTICS ITEMS
Screen Diagonal [in]
Pixels [lines]
Active Area [mm]
Sub -Pixel Pitch [mm]
Pixel Arrangement
Weight [g]
Physical Size [mm]
Display Mode
Contrast Ratio
Glass thickness (Array/CF) [mm]
Viewing Angle (CR>20)
Color Chromaticity
Cell Transparency [и]
Polarizer (CF side)
Polarizer (TFT side)
SPECIFICATIONS
40
1920 x 1080
885.6(H) x 498.15 (V) (40” diagonal)
0.15375 (H) x 0.46125 (V)
RGB vertical stripe
TYP. 1908
Reference 2D Drawing
Transmissive mode / Normally black
6500:1 Typ.
(Typical value measured at CMO’s module)
0.7 / 0.7
+88/-88(H),+88/-88(V) Typ.
(Typical value measured at CMO’s module)
R=(0.635, 0.323)
G=(0.285, 0.602)
B=(0.148, 0.056)
W=(0.280, 0.290)
(Typical value measured at CMO’s module)
4.6% Typ.
(Typical value measured at CMO’s module)
Anti-Glare coating (Haze 11%), 1030.18 (H) x 586.37(w)..
Hardness: 3H
Anti-Glare coating (Haze 11%), 1030.18 (H) x 586.37(w)..
Hardness: 3H
1.3 MECHANICAL SPECIFICATIONS
Weight
Item
Min. Typ. Max.
-- 1908 --
I/F connector mounting
position
The mounting inclination of the connector makes
the screen center within ±0.5mm as the horizontal.
Unit
g
Note
-
(2)
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position
+/- 0.5mm
Version 2.0
5 DateΚ9 Jun 2010
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
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PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment
Pin Name
1 VCC
2 VCC
3 VCC
4 VCC
5 VCC
6 GND
7 GND
8 GND
9 GND
10 ORX0-
11 ORX0+
12 ORX1-
13 ORX1+
14 ORX2-
15 ORX2+
16 GND
17 OCLK-
18 OCLK+
19 GND
20 ORX3-
21 ORX3+
22 N.C.
23 N.C.
24 GND
25 ERX0-
26 ERX0+
27 ERX1-
28 ERX1+
29 ERX2-
30 ERX2+
31 GND
32 ECLK-
33 ECLK+
34 GND
35 ERX3-
36 ERX3+
37 N.C.
38 N.C.
39 GND
40 SCL
41 N.C.
42 N.C.
43 WP
44 SDA
45 LVDS_SEL
46 N.C.
47 N.C.
48 N.C.
49 N.C.
50 N.C.
51 N.C.
Description
+12V power supply
+12V power supply
+12V power supply
+12V power supply
+12V power supply
Ground
Ground
Ground
Ground
Odd pixel Negative LVDS differential data input. Channel 0
Odd pixel Positive LVDS differential data input. Channel 0
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
Ground
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input.
Ground
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
Even pixel Negative LVDS differential data input. Channel 0
Even pixel Positive LVDS differential data input. Channel 0
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
Even pixel Negative LVDS differential data input. Channel 2
Even pixel Positive LVDS differential data input. Channel 2
Ground
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
Ground
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
EEPROM Serial Clock
No Connection
No Connection
EEPROM Write Protection
EEPROM Serial Data
High(3.3V) or open for VESA, Low (GND) for JEIDA
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Note
(1)
(1)
(1)
(3)
(1)
(1)
(1)
(3)
(3)
(4)
(3)
Version 2.0
11 DateΚ9 Jun 2010
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet V400H1-P08.PDF ] | |
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