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74LVC573A 반도체 회로 부품 판매점

OCTAL TRANSPARENT D-TYPE LATCH



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74LVC573A 데이터시트, 핀배열, 회로
74LVC573A
Description
OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS
A
Pin Assignments
The 74LVC573A provides eight transparent D-type latches. While
the latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic
levels set up at the D inputs. A buffered output-enable (OE) input
can be used to place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup
components. OE does not affect the internal operations of the
latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
These devices feature inputs and outputs on opposite sides of the
package that facilitate printed circuit board layout. The device is
designed for operation with a power supply range of 1.65V to 3.6V.
OE
D1
D2
D3
D4
D5
D6
D7
D8
GND
(Top View )
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
Vcc
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
LE
(Top Transparent View)
terminal
ind1ex
area
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
19 Q1
18 Q2
17 Q3
16 Q4
15 Q5
14 Q6
13 Q7
12 Q8
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using IOFF. The IOFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
Features
Supply Voltage Range from 1.65V to 3.6V
Sinks or Sources 24mA at VCC = 3V
CMOS Low Power Consumption
IOFF Supports Partial-Power Down Operation
Inputs or Outputs Accept Up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage
Applications
Schmitt Trigger Action at All Inputs
Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V
with VCC = 3.3V and TA = +25°C
Typical VOHV (Quiet Output Dynamic VOH) Greater than 2.0V
with VCC = 3.3V and TA = +25°C
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 250mA per JESD 78, Class I
All devices are:
Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
TSSOP-20
V-QFN4525-20
Applications
General Purpose Logic
Bus Driving
Power Down Signal Isolation
Wide Array of Products such as:
PCs, Notebooks, Netbooks, Ultrabooks
Networking Computer Peripherals, Hard Drives, CD/DVD
ROM
TV, DVD, DVR, Set Top Box
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free,
"Green" and Lead-Free.
3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC573A
Document number: DS35897 Rev. 2 - 2
1 of 11
www.diodes.com
May 2015
© Diodes Incorporated


74LVC573A 데이터시트, 핀배열, 회로
Ordering Information
74 LVC 573A XXX -13
74LVC573A
A
Logic Device
74 : Logic Prefix
LVC : Low Voltage CMOS
Function
573A :
Octal
Transparent D-
Type Latch with
3-State Outputs
Package
T20 : TSSOP-20
Q20 : V-QFN4525-20
Packing
-13 : 13” Tape & Reel
Part Number
74LVC573AT20-13
Package
Code
T20
74LVC573AQ20-13
Q20
Package
(Notes 4 & 5)
TSSOP-20
V-QFN4525-20
Package
Size
6.4mm X 6.5mm X 1.2mm
0.65mm Lead Pitch
2.5mm X 4.5mm X 0.95mm
0.50mm Lead Pitch
13” Tape and Reel
Quantity
Part Number Suffix
2500/Tape & Reel
-13
2500/Tape & Reel
-13
Notes:
4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
5. V-QFN4525-20 is a JEDEC recognized naming convention that specifies the package thickness category as V and the number 4525 describes the
package as 4.5mm X 2.5mm.
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
OE
D1
D2
D3
D4
D5
D6
D7
D8
GND
LE
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
VCC
Description
Output Enable
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Ground
Latch Enable
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Supply Voltage
Logic Diagram
OE 1
LE 11
D1 2
D
Q
C
D2 3
D
Q
C
D3 4
D
Q
C
D4 5
D
Q
C
D5 6
D
Q
C
D6 7
D
Q
C
D7 8
D
Q
C
D8 9
D
Q
C
19 Q1
18 Q2
17 Q3
16 Q4
15 Q5
14 Q6
13 Q7
12 Q8
Function Table
(Each Latch)
INPUTS
OUTPUT
OE LE
D
Q
L HH
H
LHL
L
LLX
HXX
Q0
Z
74LVC573A
Document number: DS35897 Rev. 2 - 2
2 of 11
www.diodes.com
May 2015
© Diodes Incorporated




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74LVC573A latch

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