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MC74AC373, MC74ACT373
Octal Transparent Latch
with 3-State Outputs
The MC74AC373/74ACT373 consists of eight latches with 3−state
outputs for bus organized system applications. The flip−flops appear
transparent to the data when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup time is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
• Eight Latches in a Single Package
• 3−State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
• ′ACT373 Has TTL Compatible Inputs
• These are Pb−Free Devices
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
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SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
PIN ASSIGNMENT
PIN FUNCTION
D0−D7
LE
Data Inputs
Latch Enable Input
OE Output Enable Input
O0−O7
3−State Latch Outputs
D0 D1 D2 D3 D4 D5 D6 D7
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 9
1
Publication Order Number:
MC74AC373/D
MC74AC373, MC74ACT373
TRUTH TABLE
Inputs
Outputs
OE LE Dn
On
HXX
LHL
L HH
L LX
Z
L
H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
D0 D1 D2 D3
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight D−type
latches with 3−state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2−state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
D4 D5 D6 D7
DDDDDDDD
OOOOOOOO
GGGGGGGG
LE
OE
NOTE: This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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