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IW4042B 반도체 회로 부품 판매점

Quad Clocked D-Latch



IK Semiconductor 로고
IK Semiconductor
IW4042B 데이터시트, 핀배열, 회로
TECHNICAL DATA
Quad Clocked «D» Latch
High-Voltage Silicon-Gate CMOS
IW4042B
IW4042B types contain four latch circuits, each strobed by a common
clock. Complementary buffered outputs are available from each circuit.
The impedance of the n- and p-channel output devices is balanced and all
outputs are electrically identical. Information present at the data input is
transferred to outputs Q and Q during the CLOCK level which is
programmed by the POLARITY input. For POLARITY = 0 the transfer
occurs during the 0 CLOCK level and for POLARITY = 1 the transfer
occurs during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are present.
When a CLOCK transition occurs (positive for POLARITY = 0 and
negative for POLARTY = 1) the information present at the input during
the CLOCK transition is retained at the outputs until an opposite CLOCK
transition occurs.
The IW4042B types are supplied in 16-lead hermetic dual-in-line
ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package
(E suffix), and in chip form (H suffix).
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4042BN Plastic
IW4042BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uPPIIN.Nc81o6==GmVNCDC
FUNCTION TABLE
Inputs
Clock
Polarity
00
10
11
01
Outputs
Q
D
Latch
D
Latch
1


IW4042B 데이터시트, 핀배열, 회로
IW4042B
MAXIMUM RATINGS*
Symbol
VCC
VI
VOUT
II
PD
Ptot
Tstg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Value
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
100
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC DC Supply Voltage (Referenced to GND)
VI, VOUT DC Input Voltage, Output Voltage (Referenced to GND)
TA Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2




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Quad Clocked D-Latch - IK Semiconductor