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PDF SY100E256 Data sheet ( Hoja de datos )
| Número de pieza | SY100E256 | |
| Descripción | 3-BIT 4:1 MUX-LATCH | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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3-BIT 4:1
MUX-LATCH
SY10E256
SY100E256
FEATURES
s 950ps max. data to output
s Extended 100E VEE range of –4.2V to –5.5V
s 850ps max. latch enable to output
s Separate select controls
s Differential outputs
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E256
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E256 offer three 4:1 multiplexers followed
by latches with differential outputs designed for use in new,
high-performance ECL systems. Separate Select controls
are provided for the leading 2:1 mux pairs (see block
diagram).
When the Latch Enable (LEN) is at a logic LOW, the latch
is transparent and output data is controlled by the multiplexer
select controls. A logic HIGH on LEN latches the outputs.
The Master Reset (MR) overrides all other controls to set
the Q outputs LOW.
BLOCK DIAGRAM
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1A
SEL1B
SEL2
LEN
MR
PIN CONFIGURATION
D
E
NR
D
E
NR
D
E
NR
Q0
Q0
Q1
Q1
Q2
Q2
SEL1A
SEL1B
SEL2
VEE
LEN
MR
D1c
25 24 23 22 21 20 19
26 18
27 17
28 16
1
TOP VIEW
15
PLCC
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
VCCO
Q0
PIN NAMES
Pin
D0x–D2x
SEL1A, SEL1B
SEL2
LEN
MR
Q0, Q0–Q2, Q2
VCCO
1
Function
Parallel Data Inputs
First-stage Select Inputs
Second-stage Select Input
Latch Enable
Master Reset
Data Outputs
VCC to Output
Rev.: C
Amendment: /1
Issue Date: February, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E256.PDF ] | |
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